IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 5, MAY 2016 1535 A 102–129-GHz 39-dB Gain 8.4-dB Noise Figure I/Q Receiver Frontend in 28-nm CMOS Tom Heller, Emanuel Cohen, Member, IEEE, and Eran Socher, Senior Member, IEEE Abstract— An F-band in-phase/quadrature-phase (I/Q) receiver front-end in 28-nm CMOS for chip-to-chip communication is presented. The receiver consists of a capacitively neutralized differential low-noise amplifier (LNA) chain, a passive ring mixer, zero-IF drivers, and a novel tunable transformer-based quadrature splitter. This paper discusses the effect of capacitive neutralization on common-mode stability, matching losses, and the noise performance of a differential pair. A technique for gain and noise-figure optimization by core sizing and partial neutralization is presented. The receiver exhibits a gain of 39 dB, a 3-dB RF bandwidth of 27 GHz, a noise figure between 8.4 and 10.4 dB, and a P1 dB of 3.2 dBm. The receiver front-end consumes 18 mW from a 1.0-V supply and the baseband I and Q buffers consume a total of 33 mW from a 1.5-V supply. A breakout of the LNA shows a measured gain of 21 dB, a noise figure of 8.0–9.4 dB, with a gain power efficiency of 1.2 dB/mW around 125 GHz. Index Terms—Chip-to-chip, common-mode stability, F-band, low-noise amplifier (LNA), millimeter-wave, neutralization, noise figure, passive mixer, transformer-based phase shifter, 28 nm. I. I NTRODUCTION D ATA in multi-chip systems is commonly routed via printed circuit board (PCB) copper lines. Increasing inter-chip network complexity and data rates lead to higher line density, interference, power consumption, and fault sensitivity. Some of these problems may be alleviated by switching from copper lines to wireless interconnects. As opposed to wireline networks, wireless networks are intrinsically scalable and reconfigurable: network nodes and links can be dynamically created and removed as needed, improving the network’s bandwidth allocation, power efficiency, and fault tolerance [1]. The optimal frequency band of a wireless interconnect would lie somewhere in the millimeter-wave range since it is required to transfer high data rates at short distances. The cost and form factor of a wireless interconnect can be significantly Manuscript received July 23, 2015; revised January 5, 2016 and March 1, 2016; accepted March 15, 2016. Date of publication April 14, 2016; date of current version May 10, 2016. This work was supported in part by the Intel Corporation. T. Heller was with the Electrical Engineering Department, Tel Aviv Univer- sity, Tel Aviv 69978, Israel, and also the Advanced Radio Technologies Team, Mobile and Wireless Group, Intel Corporation, Haifa 31015, Israel. He is now with Broadcom, Herzliya 46101, Israel (e-mail: t_heller@windowslive.com). E. Cohen is with the Department of Electrical Engineering, Technion–Israel Institute of Technology, Haifa 32000, Israel, and also with the Advanced Radio Technologies Team, Mobile and Wireless Group, Intel Corporation, Haifa 31015, Israel (e-mail: emcohen@ee.technion.ac.il). E. Socher is with the School of Electrical Engineering, Tel Aviv University, Tel Aviv 69978, Israel (e-mail: socher@eng.ta u.ac.il). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2547390 Fig. 1. Wireless interconnect system blocks; (right ) receiver front-end components/floor plan. reduced by integrating it with the digital chip, with the antenna dimensions typically determining the transceiver area, whether fabricated in silicon or in a dedicated substrate. A few examples follow. References [2] and [3] present transceivers at 45 and 60 GHz, respectively, both utilizing on-board Yagi–Uda antennas with dimensions of about 12 mm × 22 mm and 8.5 mm × 4 mm, respectively. At high frequencies a wire- less interconnect can be implemented as a phased-array transceiver of reasonable dimensions. Reference [4] presents a 2 mm × 2 mm adaptive 180-GHz 4 × 4 Butler matrix and a patch antenna fabricated in a dielectric substrate. On-chip antennas suffer from low radiation efficiency. Nonetheless, many works at the D-band and higher report on-chip anten- nas in order to minimize the antenna routing parasitics, which are more pronounced at high frequencies. Refer- ences [5] and [6] report a 7.4-Gb/s continuous-phase fre- quency shift-keying (CPFSK) transceiver at 120 GHz with both a bond-wire dipole antenna and an on-chip collinear broadside dipole. References [7] and [8] report 14-Gb/s on–off keying (OOK) transceivers at 240 and 260 GHz with on-chip slotted-line antennas. This work presents an F-band receiver front-end intended for on-package antenna integration. The receiver features a bandwidth of 27 GHz and a noise figure between 8.4 and 10.4 dB, and is capable of supporting dense symbol constellations and data rates at the order of tens of Gbit/s. Fig. 1 shows a block diagram of the proposed wireless inter- connect, including a packaged silicon die and two on-package antennas. An on-chip phased-locked loop (PLL) generates a V-band local oscillator (LO) signal, followed by two ×2 fre- quency multipliers, one in the transmitter and another in the receiver. This work describes the receiver, which features a differential low-noise amplifier (LNA), passive I and Q mixers, zero-IF buffers, and a transformer-based hybrid coupler. 0018-9480 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.