Background ADC Calibration in Digital Domain Cheongyuen Tsang 1 , Yun Chiu 2 , Johan Vanderhaegen 3 , Sebastian Hoyos 4 , Charles Chen 1 , Robert Brodersen 1 , Borivoje Nikoli´ c 1 1 University of California, Berkeley, CA 94704 2 University of Illinois at Urbana-Champaign,Urbana, IL 61801 3 The Bosch Research and Technology Center, Palo Alto, CA 94304 4 Texas A&M University College Station, TX 77843 Abstract— A 100MS/s pipelined ADC is digitally calibrated by a slow ΣΔ ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411kHz sinusoidal input, the peak SNDR improves from 28dB to 59dB and the SFDR improves from 29dB to 68dB. The complete 0.13μm ADC SoC occupies a die size of 3.7mm×4.7mm, and consumes a total power of 448mW. I. I NTRODUCTION Recent digital CMOS technology advancement has spurred a flurry of research activities in seeking digital adaptive tech- niques to address the inherent problem of analog impairments in a genre of mixed-mode and RF integrated circuits. In the context of pipelined ADCs, such approaches often result in relaxed matching and gain requirements of the switched- capacitor residue gain stages [1]–[4]; and in return, power efficiency and/or conversion speed can be improved. The latest effort in this regime seems to have been focusing on various nonlinear calibration schemes, as revealed by the recently reported works in the literature [5]–[7]. The general approaches of the reported calibration tech- niques thus far can be categorized into mainly three types: the statistics-based approach [5], the correlation-based approach [1]–[3], and the equalization-based ones [8], [9]. The former two share a common drawback of long calibration times, and thus are not suitable for time-variant operations [10]. In this work, we present a fast adaptive digital nonlinear calibration technique that is an extension of the work reported in [9]. We show that, with the aid of a slow ΣΔ ADC, the nonlinear residue transfer function of a pipeline stage can be fully reversed in a backend digital filter, enabling the use of simple cascode inverters as the residue amplifiers in the ADC. The resulting simplicity of the analog circuits potentially leads to a much relaxed design tradeoff between the circuit speed and accuracy, one of the most difficult aspects of analog design. II. CODE DOMAIN FILTERING APPROACH A detailed mathematical formulation of the proposed cali- bration technique is described in this section. First, we express the nonlinear transfer function of a 1.5-b/stage residue ampli- fier in the (digital) code domain as an FIR filter. It follows that the digital equivalence of the input analog voltage can be represented as a function of the output code from each pipeline stage and some circuit parameters related to matching, op-amp V o Vi 2 C2 C1 1 1 A(Vo) Vi Vo -Vr/4 Vr/4 Vr/2 -Vr/2 d=0 d=2 d=1 0 2 1 -Vr/0/Vr Fig. 1. Residue amplifier of a 1.5-b/stage pipelined ADC and its ideal (dashed line) and nonideal (solid line) voltage transfer function. gain, and offset. We will then demonstrate that a properly designed nonlinear digital filter is sufficient to correct the analog errors using a known reference signal (obtained from the ΣΔ ADC). A. Code Domain Formulation of 1.5-b Pipeline Stage Fig. 1 shows the residue amplifier of a typical switched- capacitor 1.5-b pipeline ADC stage and its voltage transfer curve. The residue voltage can be expressed as [9] V o = V i (C 1 + C 2 ) − (d − 1)V r C 2 + V os (C 1 + C 2 + C x ) C 1 (1 + C 1 + C 2 + C x A(V o )C 1 ) , (1) where, V r is the reference voltage, C x is the summing- node parasitic capacitance, V os is the lumped offset voltage, A(V o ) is the signal-dependent op-amp gain, and d is the digital decision of the current stage that assumes a value of 0, 1, or 2. The term A(Vo)C1 C1+C2+Cx is the loop gain of the residue amplifier. After dividing both sides of (1) by V r , a digital representation is obtained, D i ( C 1 + C 2 C 1 )= D o (1 + C 1 + C 2 + C x C 1 1 A(D o ) ) +(d − 1)( C 2 C 1 ) − D os ( C 1 + C 2 + C x C 1 ), (2) where, D i = Vi Vr , D o = Vo Vr , and D os = Vos Vr . Equivalently, (2) can be approximated by a power series expansion [11]: D i = D o α 1 + D o 2 α 2 + D o 3 α 3 + D o 4 α 4 + ... +(d − 1)β − D os γ, (3) where, α k = f k (C 1 ,C 2 ,C x ,A(D o )), β =( C2 C1+C2 ), γ = ( C1+C2+Cx C1+C2 ). Note that the truncated version of (3) resembles 301 IEEE 2008 Custom Intergrated Circuits Conference (CICC) 978-1-4244-2018-6/08/$25.00 ©2008 IEEE 12-3-1