Efficient Exact Spare Allocation via Boolean Satisfiability Fang Yu 2 , Chung-Hung Tsai 2 , Yao-Wen Huang 12 , Hung-Yau Lin 1 , D. T. Lee 2 , Sy-Yen Kuo 1 1 Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan. sykuo@cc.ee.ntu.edu.tw 2 Institute of Information Science, Academia Sinica, Taipei 115, Taiwan { yuf,chtsai, ywhuang, dtlee}@iis.sinica.edu.tw Abstract Fabricating large memory and processor arrays is subject to physical failures resulting in yield degradation. The strategy of incorporating spare rows and columns to obtain reasonable production yields was first proposed in the 1970s, and continues to serve as an important role in recent VLSI developments. Since the spare allocation problem (SAP) is NP- complete but requires solving during fabrication, an efficient exact spare allocation algorithm has great value. Here we propose a new Boolean encoding of SAP and a new SAT- based exact algorithm SATRepair. We used a realistic fault distribution model to compare SATRepair’s performances against BDDRepair and those of algorithms found in the literature. We suggest that a) our novel Boolean encoding of SAP allows for the development of efficient exact SAP algorithms, and b) our SAT-based algorithm outperforms previous algorithms, especially for large problems. 1. Introduction Repairable arrays continue to serve as an important component in recent VLSI developments, and not only because fabrication imperfections grow proportionally with chip size and density. As today’s photolithography techniques approach physical limits in terms of density growth and device miniaturization, future fabrication will depend on such new technologies as Next Generation Lithography (NGL) techniques and Chemically Assembled Electronic Nanotechnology (CAEN). NGL and CAEN share one major disadvantage: the likelihood of having significantly higher defect densities; an expected defect density of as high as 10 percent requires efficient fault repair algorithms [32]. In addition, in 2001 the International Technology Roadmap for Semiconductors (ITRS) [1] reported that SoCs have moved from logic-dominant to memory-dominant chips (see Figure 1), and will embed memories of increasing sizes. This trend, which was confirmed by the ITRS 2003 report [2], implies that SoC yields are dominated by memory yields; hence, SAP algorithm efficiency directly affects today’s SoC yields. This holds true not only for SoCs, but also for current state-of-the-art processors in general. For example, in the Intel Itanium 2 Processor, the 9MB third-level on-die cache contains over 90 percent of all the 592M transistors on the 432mm 2 die [37]. Therefore, as feature sizes shrink to single digit nanometer dimensions and memory takes up a major area share of SoCs and advanced processors, defect tolerance is becoming increasingly important. A common treatment since the 1970s has been to use redundancy to replace faulty modules (see for example Schuster [35]). This strategy is most suitable for uniformly structured chips such as memory arrays, in which rows and columns of spare cells can be employed to replace faulty ones that occur during fabrication. The goal of the spare allocation (sometimes referred to as memory reconfiguration) problem (SAP) is to find an assignment of spare rows and columns to faulty rows and columns such that all faulty cells