HEPSIM: an ESL HW/SW Co-Simulator/Analysis Tool for Heterogeneous Parallel Embedded Systems Daniele Ciambrone, Vittoriano Muttillo, Luigi Pomante, Giacomo Valente Università degli Studi dell’Aquila – Center of Excellence DEWS L’Aquila, ITALY {daniele.ciambrone, vittoriano.muttillo}@graduate.univaq.it, {luigi.pomante, giacomo.valente}@univaq.it Abstract— Heterogeneous devices are becoming widely diffused in the embedded system domain, mainly because of the opportunities to increase application execution performance and, at the same time, to substantially reduce energy consumption. In such a context, this work faces the role of HW/SW co- simulators/analysis tools for embedded systems based on heterogeneous parallel architectures. In particular, it presents a SystemC-based tool for functional/timing HW/SW co-simulation and analysis within a reference ESL HW/SW co-design flow. The description of the main features of the tool, the main design and integration issues and an illustrative case study represent the core of the paper. Electronic System-Level Design; HW/SW Co-Design; Parallel Embedded Systems; Heterogeneous Systems I. INTRODUCTION The growing complexity of nowadays embedded digital systems, especially if based on modern System-on-Chip (SoC) adopting explicit heterogeneous parallel architectures (e.g. [1][2][3]), and their reduced time-to-market have radically changed the common design methodologies. Traditional design approaches, based on independent design of HW/SW components are no longer sufficient to efficiently exploit subparts of such SoCs. For this, HW/SW co-design methodologies, where designers can early check system-level constraints and evaluate cost/performance trade-offs, are of renovated relevance. In fact, these kinds of methodologies are able to lead the system-level analysis by means of proper models, metrics, and tools, supporting the designer in all those activities that are normally entrusted only to his experience. In particular, HW/SW co-simulation and analysis tools cover a very important role in every HW/SW co-design flow, because they allow a fast analysis of the system properties. In such a context, this work presents a SystemC-based tool for functional/timing HW/SW co-simulation and analysis integrated into a reference Electronic System-Level (ESL) HW/SW Co-Design methodology targeting heterogeneous parallel embedded systems. The main contribution is to describe the main features of the tool, and to describe the main design and integration issues with respect to a whole comprehensive ESL HW/SW Co-Design framework [17]. This paper is organized as follows. Section II describes some relevant ESL co-simulation and analysis tools. Section III briefly presents the reference ESL HW/SW co-design flow while Sections IV and V describe the main design and implementation issues. Then, Section VI presents an illustrative case study to show the main features of the proposed tool. Finally, Section VII draws out some conclusions and outlines the future work. II. C++/SYSTEMCBASED TOOLS In the recent years, in the Electronic Design Automation (EDA) domain, there has been a push towards the development of ESL tools able to span the complete design space across hardware and software boundaries. A lot of them are placed within a framework of HW/SW Co-Design to perform functional and timing simulations by using SystemC [4] as ESL description language. Some of the most relevant ones, both commercial and academic, are briefly described below. As a meaningful representative of available commercial tools, CoFluent Studio [5] by Intel is a modeling and simulation environment for early high-level design space exploration. It allows capturing the application functionality, the HW architecture and their mapping. Application models are specified as networks of communicating processes. HW platforms can be graphically assembled out of generic processing and interconnection elements. Once performed a manual mapping among application and architecture elements, CoFluent can generate a SystemC Transaction-Level Model (TLM) of the resulting system for simulation, analysis, and virtual prototyping. Another interesting SystemC-based commercial tool is SpaceStudio [6] by SpaceCodesign. By using it, designers can create process-based SystemC application models out of predefined library blocks or by importing and wrapping existing C, C++ or SystemC code. Next, a system architecture can be graphically assembled, and the application can be manually mapped by dragging application blocks onto previously allocated processors. As a result, SpaceStudio will generate a SystemC TLM of the defined platform. All SystemC application models and TLMs generated through SpaceStudio can be simulated for analysis and performance evaluation. Among academic simulators, it is possible to find SystemCoDesigner (System-Level Hardware- Software-Co-Design Tool) [14]. It is a software tool for (semi)automatic design space exploration at system-level. The goal is to allocate resources and bind a task graph onto these allocated resources. The designer has to specify the task graph, the architecture template (as a graph), as well as all possible bindings of the nodes in the task graph onto the resources in the architecture template. Finally, eSSYn (Embedded Software 2018 7 th MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING (MECO), 11-14 JUNE 2018, BUDVA, MONTENEGRO 978-1-5386-5683-9/18/$31.00 ©2018 IEEE