W4G.3.pdf OFC 2017 © OSA 2017 A Chip-Scale Heterodyne Optical Phase-Locked Loop with Low-Power Consumption Arda Simsek 1 , Shamsul Arafin 1 , Seong-Kyun Kim 1 , Gordon Morrison 2 , Leif A. Johansson 2 , Milan Mashanovitch 2 , Larry A. Coldren 1 , and Mark J. Rodwell 1 1 Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, 93106, USA. 2 Freedom Photonics LLC, Santa Barbara, CA, 93117, USA ardasimsek@ece.ucsb.edu Abstract: A chip-scale heterodyne optical phase-locked loop, consuming only 1.3 W of electrical power, with a maximum offset locking frequency of 17.4 GHz is demonstrated. The InP-based photonic integrated receiver circuit consumes only 166 mW. OCIS codes: (250.5300) Photonic integrated circuits; (060.2840) Heterodyne; Optical phase-locked loop; (060.5625) Radio Frequency Photonics 1. Introduction and Design of the Heterodyne OPLL There has been significant effort for realizing highly-integrated chip-scale optical phase-locked loops (OPLLs) in the last decade along with the development in the photonic integration. Traditional free space optics creates loop delays in the order of tens of nanoseconds, which makes the loop bandwidth small. However, with the improvement in photonic integration, OPLLs can be realized with loop bandwidths in the order of hundreds of MHz [1] or even more than 1 GHz [2]. This makes OPLLs attractive and they can be used in a wide range of applications including coherent receivers, high sensitivity detection, laser linewidth narrowing, millimeter and THz wave generation and optical frequency synthesis [3-5]. In previous works, offset locking ranges up to 25 GHz [6], large loop bandwidth exceeding 1 GHz [2] and residual OPLL phase noise variance as low as 0.03 rad 2 [1] were demonstrated for the chip-scale OPLLs. However, these OPLLs consume almost 3 W of electrical power [2], being unsuitable for the real life applications. In this work, a chip-scale heterodyne OPLL with a total power consumption of 1.3 W is designed and demonstrated utilizing a novel indium phosphide (InP)-based photonic integrated circuit (PIC) and commercial- off-the-shelf (COTS) electronic ICs. The PIC receiver contains a widely-tunable (50 nm) compact Y-branch laser, a 180° hybrid (MMI) and two photodiodes. This is offset locked to narrow-linewidth (100 kHz) external-cavity laser (ECL) up to a range of 17.4 GHz with an RF synthesizer. The low power consumption PIC is integrated with COTS electronic ICs in order to realize the highly-integrated OPLL. An optical microscope image and the schematic of the receiver PIC is shown in Fig. 1(a) and (b), respectively. The PIC incorporates a compact Y-branch laser formed between a high-reflectivity coated back mirror and a pair of Vernier tuned front mirrors. The output from one mirror leads to the coherent receiver used for offset locking, while the other output forms the optical output signal from the backend integrated system. The Y-branch laser has a compact cavity with short gain and mirror sections, requiring low current and therefore low drive power. It is tuned via Vernier effect and has been designed for high efficiency at 30º C ambient. The measured tuning range exceeds 50 nm with >50 dB side-mode suppression ratio. The low power receiver PIC is connected with SiGe-based COTS ICs including a limiting amplifier and digital XOR as a mixer/phase detector. The limiting amplifier has a 3-dB bandwidth of 17 GHz with 30 dB of differential gain. The digital XOR operates up to at least 12.5 GHz input RF frequencies. The limiting amplifier limits the signal coming from photodiode pair to logic levels, which enables the system to be insensitive to any optical intensity fluctuations. A second order dual-path loop filter was used to get high loop bandwidth. This was achieved by employing a fast feedforward path which increases the system frequency acquisition range. Fig. 1(b) and (c) displays the architecture and a microscope image of the whole OPLL system, respectively. The PIC, electronic ICs and the loop filter are all integrated on an aluminum nitride (AlN) carrier, and wire-bonded. The system size is approximately 1.8 cm by 1.6 cm. Total delay is less than 300 ps, and the loop bandwidth is approximately 500 MHz. 2. Results and Discussion Total power consumption of the OPLL system excluding the thermoelectric controller power is measured to be 1.318 W, which is the lowest power consumption for an OPLL to the best of authors’ knowledge. In this system, the PIC consumes only 166 mW, and the COTS control electronics consume 1.152 W. Table 1 demonstrates the power consumption of every component and the total power consumption. This result is considerably better than the previous result reported in [2].