Materials Science and Engineering B61 – 62 (1999) 497 – 501 Design of a 600 V silicon carbide vertical power MOSFET D. Planson *, M.L. Locatelli, F. Lanois, J.P. Chante CEGELY, UPRES -A CNRS n °5005, INSA de Lyon, Bat 401 20, A. A. Einstein, F -69621 Villeurbanne Cedex, France Abstract Silicon carbide (SiC) owns very interesting properties to fulfil the requirements of new power electronic applications. This paper reports the design of two vertical power MOSFETs, able to sustain a forward blocking voltage of 600 V. In order to evaluate the performance, 2D-simulations were performed taking into account the current technological constraints and the SiC materials parameters. © 1999 Elsevier Science S.A. All rights reserved. Keywords: Silicon carbide; Vertical MOSFET; 2D-simulation 1. Introduction Excellent physical properties of the silicon carbide (SiC) semiconductor material offer the opportunity to realize a breakthrough on the performance of the high power, high temperature and high frequency electronic applications [1,2]. Electronic system designers search for improving the features of the components to fulfil the new and more and more exacting applications, in terms of density, speed and temperature constraints. These are the reasons for the nowadays extensive and numerous research studies world-wide on SiC. SiC could become in the near future a substitute for the silicon unipolar devices in the range over 200 V. The time has come to think about the design of the new components taking into account the material parame- ters and the technological feasibility. This paper presents the simulated electrical character- istics of two vertical power MOSFETs. Such kind of transistors have already been realised [3,4]. The aim is to achieve a realistic estimation of the electrical perfor- mance of a 600 V SiC unipolar transistor using the finite element software MEDICI taking into account the current severe technological constraints for both commercially available silicon carbide polytypes (6H and 4H-SiC). 2. Structure description Due to the lack of dopant diffusion into silicon carbide, non-classical ways for the realisation of such vertical transistors must be used. In this paper two vertical structures have been studied. Fig. 1 presents the U-MOSFET structure, so-called due to the shape of the groove, and also the range of variation for all physical parameters. Two successive epitaxial (n- and p-type, respectively) layers are grown on a highly doped sub- strate. N-type implantation is required to realize the source. Plasma etching allows the realisation of the groove before the gate oxide deposition and the gate metallization. Source metallization is patterned on the top side while the drain metallization is realised on the whole surface of the back side of the wafer. For this structure, the main technology parameters are the slope of the trench and the length at the bottom of the trench. In agreement with our etching results [5] the slope could be varied in the range 15–65°, this angle is defined with respect to the vertical axis. The total depth of the groove is given by the thickness of the p-type epitaxial layer plus an additional removal of the SiC to assure the good operation of the transistor, this one was fixed to 0.2 m. Plasma etching experimental re- sults show that an ‘overetch’ appears at the bottom of the groove and we assume that it is proportional to the total etch depth. This will be later called trenching and will be considered for the small angles in our simula- tions. Another important geometrical parameter is the length at the bottom of the trench, depending mainly on the lithography performance. * Corresponding author. Fax: +33-04-7243-8530. E-mail address: planson@cegely.insa-lyon.fr (D. Planson) 0921-5107/99/$ - see front matter © 1999 Elsevier Science S.A. All rights reserved. PII:S0921-5107(98)00461-9