Received: 26 March 2019 Revised: 2 August 2019 Accepted: 8 August 2019 DOI: 10.1002/ett.3747 RESEARCH ARTICLE An expandable topology with low wiring congestion for silicon interposer-based network-on-chip systems Sajed Dadashi 1 Midia Reshadi 1 Akram Reza 2 Ahmad Khademzadeh 3 1 Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran 2 Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran 3 Iran Telecommunication Research Center, Tehran, Iran Correspondence Midia Reshadi, Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran 14778 93855, Iran. Email: reshadi@srbiau.ac.ir Abstract In 2.5D stacking technology, multiple chips have stacked side-by-side on a sili- con interposer layer. The network-on-chip in the central processing unit (CPU) layer makes it possible to connect processing cores to each other. The interposer layer prepares the connection between the CPU cores and other chips such as memory chip. The memory chip usually contains several segments stacked ver- tically. The network-on-chip can be extended to the interposer layer to make use of unused routing resources of the interposer. Applying an efficient topology and deadlock-free routing algorithm on the CPU layer and interposer layer is essen- tial. In this paper, a new topology and routing algorithm are proposed to use on the CPU layer as well as on the interposer layer for creating a uniform inter- connection network to decrease delay and power consumption. This topology is scalable and can be used simply for extensive networks. Most of interposer layer topologies are not scalable and have a lot of crossed links. Moreover, it is required to increase the degree of routers connected to memory segments. The proposed topology uses a few crossed links compared to other proposed interposer layer topologies. There will be some similar small sub-networks that fairly connected together with intermediate routers. Furthermore, this topology can be extended in a hierarchical manner. 1 INTRODUCTION There are two types of stacking technologies to integrate multiple silicon chips. 1 Three-dimensional (3D) stacking tech- nology makes it possible to stack various dies together. 2 It takes multiple silicon chips and places one on top of the other. 3,4 The 3D stacking has some problems such as heat dissipation. 5 Another stacking approach is two-and-a-half-dimensional (2.5D) stacking technology that places multiple chips side-by-side on a silicon interposer layer. 6 In fact, an interposer is on top of the package of a 2.5D system. Different chips can be mounted on the interposer layer. The 2.5D approach allows functional blocks to be designed separately. 7 This technology can decrease metal connection routes and can solve many of 3D stacking problems. It prepares the capability for system components to be designed simultaneously. 8 Silicon interposers can be used in many devices such as FPGAs to reduce design complexity. Applying this type of stacking can improve efficiency and decrease the implementation cost. 9 Intermediate stages of packaging are no longer needed and the system occupies less space. It is feasible to design the chips independently with reusable components. 10 The inter- poser is actually a silicon chip with upward metal layers. Using an interposer layer has many benefits such as considerable electrical property, low cost and high wiring capacity. 11 A many-core central processing unit (CPU) alongside a vertically stacked memory chip is a common integration. 12 For example, the memory segments can be positioned on the right and left sides of the CPU chip on the interposer layer. 13 Trans Emerging Tel Tech. 2019;e3747. wileyonlinelibrary.com/journal/ett © 2019 John Wiley & Sons, Ltd. 1 of 20 https://doi.org/10.1002/ett.3747