Fabrication and Circuit Modeling of NMOS Inverter Based on Quantum Dot Gate Field-Effect Transistors SUPRIYA KARMAKAR, 1,2,3,4 JOHN A. CHANDY, 1 MUKESH GOGNA, 1 and FAQUIR C. JAIN 1 1.—Department of Electrical and Computer Engineering, University of Connecticut, 371, Fairfield Way, U-2157, Storrs, CT 06269-2157, USA. 2.—Present address: Intel Corporation, Hillsboro, OR 97124, USA. 3.—e-mail: mr.karmakar@yahoo.com. 4.—e-mail: suk06001@engr.uconn.edu This paper presents the fabrication of a negative-channel metal–oxide–semi- conductor (NMOS) inverter based on quantum dot gate field-effect transistors (QDG-FETs). A QDG-FET produces one intermediate state in its transfer characteristic. NMOS inverters based on a QDG-FET produce three states in their transfer characteristic. The generation of the third state in the inverter characteristic makes this a promising circuit element for multivalued logic implementation. A circuit simulation result based on the Berkley simulation (BSIM) circuit model of the QDG-FET is also presented in this paper, pre- dicting the fabricated device characteristic. Key words: Quantum dot gate FET, three-state FET, NMOS inverter, three- state NMOS inverter INTRODUCTION Metal–oxide–semiconductor field-effect transis- tors (MOSFETs) produce only two states in their transfer characteristics. According to Moore’s law, electronic industries are always thinking about miniaturization of electronic devices. Starting from small-scale integration (SSI) technology, silicon industry has already achieved ultralarge-scale integration (ULSI) technology and is now in nano- meter (nm)-scale integration. The degree of inte- gration can be increased by decreasing the size of the individual devices as well as increasing their bit-handling capacity. Multivalued logic circuits can be implemented based on quantum dot gate field- effect transistors. Until now, multivalued logic has not reached maturity because of the lack of proper semiconductor devices. Researchers are trying to implement multivalued logic using conventional field-effect transistors (FETs) with different architectures. 1–6 However, the main problem is the complication in the circuit design as well as delay, rise time, fall time, and power dissipation. New devices are required for multivalued logic implementation. Different promis- ing semiconductor devices such as resonant tunnel- ing diodes (RTDs), 7–9 resonant tunneling transistors (RTTs), 10–13 modulation-doped field-effect transistors (MODFETs), 14–16 and high-electron-mobility tran- sistors (HEMTs), 17–19 which produce negative dif- ferential resistance (NDR), have been proposed for multivalued logic implementation. Since the basic operation principle of these devices is band-to-band tunneling of charge carriers, the main problem with these devices is the high valley current because of charge leakage between different bands. In QDG-FETs, the intermediate state is gener- ated because of charge leakage from the inversion channel to the quantum dots deposited on top of the gate insulator. As the gate voltage is increased, the tunneling of charge carriers from the inversion channel to the quantum dots in the gate region increases the threshold voltage of the device, which makes the drain current independent of the gate voltage in the intermediate range. This phenome- non produces the third state between the ‘‘ON’’ and ‘‘OFF’’ states of the conventional FET. Since the quantum dots in the gate region are surrounded by a high-bandgap cladding layer, the probability of charge leakage is less than for other NDR devices mentioned in the previous paragraph. (Received March 10, 2011; accepted April 19, 2012; published online May 10, 2012) Journal of ELECTRONIC MATERIALS, Vol. 41, No. 8, 2012 DOI: 10.1007/s11664-012-2116-4 Ó 2012 TMS 2184