Materials Science and Engineering B 124–125 (2005) 494–498 Oxidation effects on transport characteristics of nanoscale MOS capacitors with an embedded layer of silicon nanocrystals obtained by low energy ion implantation J. Grisolia a,∗ , M. Shalchian b,c , G. BenAssayag b , H. Coffin b , C. Bonafos b , S. Schamm b , S.M. Atarodi c , A. Claverie b a D´ epartement de G´ enie Physique, LNMO-INSA, 135 Avenue de Rangueil, 31077 Toulouse, France b nMat Group, CEMES-CNRS, 29 rue Jeanne Marvig, 31055 Toulouse, France c Electrical Engineering Department, Sharif University of Technology, P.O. Box 11365-8639, Tehran, Iran Abstract In this paper, we have studied the effect of annealing under slightly oxidizing ambient (N 2 +O 2 ) on the structural and electrical characteristics of a limited number of silicon nanoparticles embedded in an ultra-thin SiO 2 layer. These nanoparticles were synthesized by ultra-low energy (1 keV) ion implantation and annealing. Material characterization techniques including transmission electron microscopy (TEM), Fresnel imaging and spatially resolved electron energy loss spectroscopy (EELS) have been used to evaluate the effects of oxidation on structural characteristics of nanocrystal layer. Electrical transport characteristics have been measured on less than one hundred nanoparticles by exploiting a nanoscale MOS capacitor as a probe. Top electrode of this nanoscale capacitor (100 nm × 100 nm) was patterned over the samples by electron-beam nanolithography. Room temperature I–V characteristics of these structures exhibit discrete current peaks, which have been interpreted by quantized charging of the nanoparticles and electrostatic interaction between the trapped charges and the tunneling current. The effects of progressive oxidation on these current features has been studied and discussed. © 2005 Elsevier B.V. All rights reserved. Keywords: Silicon nanoparticles; Quantum dots; Coulomb blockade; MOS 1. Introduction Quantum electronic devices are one of the future alternatives of the conventional electronic devices [1–3]. In these devices, the discrete nature of electrical charges in the form of Coulomb blockade effect and single-electron tunnelling effect can be exploited to reduce the cost per functionality for the future nanoscale integrated circuits. However, these features must oper- ate at room temperature to make single-electron devices feasible for a wide range of practical applications. In this purpose, silicon nanoparticles (ncs) appear to be an attractive candidate for room temperature single-electron mem- ory in which addition or subtraction of a single electron can rep- resent a bit of data. Memory devices consisting of a metal-oxide- semiconductor field-effect transistor (MOSFET) with nanocrys- tals embedded within the gate oxide has already been identified ∗ Corresponding author. Tel.: +33 5 61 55 96 58; fax: +33 5 61 55 96 97. E-mail address: jeremie.grisolia@insa-toulouse.fr (J. Grisolia). as promising candidates for high storage density and low power memory applications [4–5]. Indeed, the use of a charge-storage floating-gate made of mutually isolated nanocrystals instead of a continuous poly-Si layer reduces charge losses through the underlying tunnel oxide by defect paths, and therefore allows for the down-scaling of the tunnel oxide. For device operation in the direct tunneling regime, a fine control of the nanocrys- tal location is absolutely required since a change of less than 1 nm in tunnel oxide thickness dramatically affects operating condition (write/erase times and voltages) and data retention characteristics [6–7]. Recently, numerous techniques have been developed for the fabrication of silicon nanoparticles within a thin oxide layers including chemical vapor deposition (CVD) [8], ion implantation [9] and aerosol deposition [10]. Among these techniques, ultra-low energy ion beam synthesis (ULE- IBS) is one of the most promising. In particular, the ULE-IBS fabrication technique is very attractive because of its ability to form a 2D layer of isolated of nanocrystals and its compati- bility with standard CMOS technology. In practice, high dose (typically ≥10 16 cm -2 ) Si implantation with the 1 keV energy 0921-5107/$ – see front matter © 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.mseb.2005.08.082