Calibration of Nonlinear Radix in Pipelined Analog-to-Digital Converters Using a Correlation Algorithm Hamed Aminzadeh * , Morteza Rajabzadeh † * Department of Electrical Engineering, Payame Noor University, 19395-4697, Tehran, Iran † ECE Department, Quchan University of Advanced Technology, Quchan, Khorasan Razavi, 9471784686, Iran Abstract—The devices used in current integrated circuits technology are mostly non-linear. This issue makes the matching between such devices almost impossible. In pipelined analog- to-digital converters (ADC), this implies that achieving to the accuracies more than those allowable by the error sources is impossible without using an effective calibration technique. It can be shown by simulations that the number of the front-end stages that should be calibrated is larger than the difference of the maximum achievable bits without calibration and the required bits of the converter. In this paper, a discussion is provided on the modeling of the important error sources of the pipelined ADC in gain of the stages, and then, a novel approach is proposed for the non-linear calibration of the ADC stages. Index Terms—pipelined analog-to-digital converters, Digital calibration. I. I NTRODUCTION Fig. 1 shows the block diagram of a conventional pipelined ADC. It is composed of N consecutive stages, each of which is comprised of a k-bit sub-analog-to-digital converter (sub- ADC), a k-bit sub-digital-to-analog converter (sub-DAC), an analog differentiator, an amplifier and a sampler. To imple- ment this architecture, the k-bit sub-DAC, analog subtractor, amplifier and sampler are all implemented by a basic block named MDAC. The MDAC consists of an op-amp, and a number of capacitors and switches. The sub-ADCs at the input of the stages are realized by some comparators, which can be designed using an arrangement of some transistors. At each stage, an estimate of the input is converted to digital codes by the sub-ADC with a low accuracy, and the result is converted back to an analog signal by the sub-DAC. This converted signal is then subtracted from the input signal by the subtractor. The residue signal is equivalent to the quantization noise resulting from analog to digital conversion at that stage. This residual noise is then amplified and transferred to the next stage to be processed further for more accuracy. The main advantage of pipelined ADCs is their ability for sequential analysis of the different data samples at different stages. In other words, when the MDAC of one particular stage is amplifying the residual noise of a sample, the MDAC at previous stage is sampling the same sample. This increases the conversion rate to a limiting factor based on the time required for each stage to propagate the analog signal. The comparators have a large offset, leading to missing of some information due to output saturation. To avoid this (a) (b) Fig. 1. Block diagram of a conventional pipelined ADC and its transfer function (a) Block diagram, (b) 1.5-bit transfer function. Fig. 2. Block diagram of a functional pipelined ADC [3] drawback, two semi-calibration methods are used in practice: analog error correction and digital error correction. In the former, the gain of the stages is reduced in order to avoid the saturation of the MDAC stages due to the false decision of the comparators, and some stages are added at the output of the converter to compensate the gain reduction. In the latter, the number of the comparators is increased at each of the stages [1], [2]. INTERNATIONAL JOURNAL OF SYSTEMS APPLICATIONS, ENGINEERING & DEVELOPMENT Volume 10, 2016 ISSN: 2074-1308 330