This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY 1 Fan-Out Wafer-Level Packaging for Heterogeneous Integration John H. Lau , Fellow, IEEE , Ming Li, Margie Li Qingqian, Tony Chen, Iris Xu, Qing Xiang Yong, Zhong Cheng, Nelson Fan, Eric Kuah, Zhang Li, Kim Hwee Tan, Yiu-Ming Cheung, Member, IEEE, Eric Ng, Penny Lo, Wu Kai, Ji Hao, Koh Sau Wee, Jiang Ran, Cao Xi, Rozalia Beica, Sze Pei Lim, N. C. Lee, Cheng-Ta Ko, Henry Yang, Yu-Hua Chen, Mian Tao, Jeffery Lo, and Ricky S. W. Lee, Fellow, IEEE Abstract— The design, materials, process, fabrication, and reliability of a heterogeneous integration of four chips and four capacitors by a fan-out wafer-level packaging (FOWLP) method are investigated in this paper. Emphasis is placed on the application of a new assembly process for fabricating the redistribution layers of the FOWLP. Reliability assessments, such as the thermal cycling and drop test, are also performed. Index Terms—Fan-out wafer-level packaging (FOWLP), het- erogeneous integration, redistribution layers (RDLs), system-in- a-package (SiP). I. I NTRODUCTION M OORE’S law [1] has been driving the system-on-a- chip (SoC) platform. Especially, in the past 10 years, SoCs have been very popular for smartphones, tablets, and so on. SoCs integrate different-function ICs into a single chip for a system or a subsystem. Typical SoC examples are Apple’s application processors A10 and A11. A10 is manufactured by TSMC using its 16-nm process technology, while A11 is using its 10-nm process technology. Comparing to A10, the A11 consists of more functions such as the neural engine for face ID. However, the chip area (10 mm × 8.7 mm) of A11 is about 30% smaller than that (11.6 mm × 10.8 mm) of A10 due to Moore’s law, i.e., the feature size is from 16 down to 10 nm. Why is heterogeneous integration of such great inter- est [2]–[12]? One of the key reasons is because the end of Moore’s law is fast approaching, and it is more and more Manuscript received March 9, 2018; revised May 15, 2018; accepted June 6, 2018. Recommended for publication by Associate Editor C. Lee upon evaluation of reviewers’ comments. (Corresponding author: John H. Lau.) J. H. Lau, M. Li, M. L. Qingqian, N. Fan, E. Kuah, Y.-M. Cheung, E. Ng, P. Lo, W. Kai, and J. Hao are with ASM Pacific Technology Ltd., Hong Kong (e-mail: john.lau@asmpt.com). T. Chen, I. Xu, Z. Li, and K. H. Tan are with Jiangyin Changdian Advanced Packaging Company Ltd., Jiangyin 214431, China. Q. X. Yong, Z. Cheng, K. S. Wee, J. Ran, and C. Xi are with Huawei Technologies Company Ltd., Shenzhen 51800, China. R. Beica is with Dow Chemical Company, Boston, MA 01752 USA. S. P. Lim and N. C. Lee are with Indium Corporation, Utica, NY 13502 USA. C.-T. Ko, H. Yang, and Y.-H. Chen are with Unimicron Technology Corporation, Hsinchu 304, Taiwan. M. Tao, J. Lo, and R. S. W. Lee are with The Hong Kong University of Science and Technology, Hong Kong. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCPMT.2018.2848649 difficult and costly to reduce the feature size (to do the scaling) to make SoCs. Heterogeneous integration contrasts with SoCs and uses a packaging technology to integrate dissimilar chips with different functions from different foundries, wafer sizes, and feature sizes (as shown in Fig. 1) into a system or a subsystem, rather than integrating most of the functions into a single chip and going for a finer feature size. For the next few years, we will see more of a higher level of heterogeneous integration, whether it is for time to market, performance, form factor, power consumption, signal integrity, or cost. Heterogeneous integration is going to take some of the market shares away from SoCs on high-end applications, such as high-end smartphones, tablets, wearables, networking devices, telecommunications, and computing devices. System-in-a- package (SiP) [13]–[23] is similar to heterogeneous integration except less dense, larger pitch, and simpler. How should these dissimilar chips talk to each other, however? The answer is: redistribution layers (RDLs) [24], [25]. How should those RDLs be made? In this paper, we use the fan-out wafer-level packaging (FOWLP) technology. In this paper, the feasibility of a chip-first and die face- down FOWLP of a heterogeneous integration of four chips and four capacitors is demonstrated. In order to have a very low-profile package and save the expensive epoxy molding compound (EMC) cost, a new process is developed to fabricate the RDLs. Reliability assessments, such as the thermal cycling and shock (drop) test, are performed. II. TEST CHIPS Figs. 2–4 show the test chips under consideration. The layout of the large test chip is shown in Fig. 2, and the fabricated large chip is shown in Fig. 3. It can be seen that the larger chip sizes are 5 mm × 5 mm × 150 μm, and there are 160 pads with a pitch = 100 μm (the inner rows). The SiO 2 passivation opening of the Al-pad is 50 μm × 50 μm, and the size of the Al-pad is 70 μm × 70 μm. The dimensions of the small chip are 3 mm × 3 mm × 150 μm, and the fabricated chip is shown in Fig. 4. It can be seen that there are 80 pads and are on 100-μm pitch (inner rows). The cross section and dimensions of the pads of the small chip are the same as those of the large chip. III. TEST PACKAGE Fig. 5 schematically shows the test package under consid- eration. The dimensions of the test package are: 10 mm × 2156-3950 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.