Design Optimization of Microstrip Lines with Via Fences through Surrogate Modeling based on Polynomial Functional Interpolants José E. Rayas-Sánchez and Noel Vargas-Chávez Department of Electronics, Systems and Informatics, ITESO (Instituto Tecnológico y de Estudios Superiores de Occidente), Tlaquepaque, Jalisco, 45604 Mexico http://iteso.mx/~erayas e-mail: erayas@iteso.mx Abstract — A common technique to reduce crosstalk between microstrip lines consists of using via fences or guard traces. However, via fences may significantly increase the amount of reflections at the signaling microstrip lines. We propose an EM- based design optimization method to achieve reduction of crosstalk and transmission losses by the use of via fences without a significant deterioration of impedance matching at the signaling microstrip lines. Our method exploits surrogate models using polynomial-based functional interpolants. We start from a zero-order model that is as simple as a fixed EM model response. This zero-order model is enhanced by multidimensional polynomial interpolants around a reference base point in the design space. The polynomial approximation is a function of the design variables, and it is used to interpolate highly accurate EM responses in a region of interest around the selected base point. Global optimum values for the surrogate model weighting factors are efficiently obtained in closed form. By optimizing the surrogate model, we efficiently find an optimal performance for the microstrip lines with via fences. Index Terms — Crosstalk, microstrip via fences, guard traces, high-speed interconnects, signal integrity, surrogate modeling, space mapping, EM-based optimization. I. INTRODUCTION The relevance of signal integrity and high-speed interconnect design has dramatically augmented in the last two decades, motivated by the well-established trends of higher data bit rates on denser routing topologies of complex interconnects at both the PCB and package level. Interconnect engineers must creatively satisfy increased performance demands under severe budget constraints. Crosstalk is one major problem inherent to the above trends and aggravated by the continued miniaturization of PCB and packaging technologies. A traditional technique to minimize crosstalk between adjacent microstrip lines on PCBs consists of using via fences or guard traces, which can take the form of intermediate microstrip lines periodically grounded by plated via holes. It has been demonstrated, experimentally and by full-wave EM simulations, that inserting via fences between microstrip lines effectively reduces crosstalk [1,2] as well as transmission losses [3]. These benefits, however, may come along with a significant increase in the amount of reflections at the signaling microstrip lines due to deterioration of impedance matching [4]. This work was supported in part by CONACYT (Consejo Nacional de Ciencia y Tecnología, Mexican Government) under Grant CB-083981, and in part by Intel Guadalajara Design Center. In this paper, we propose an EM-based design optimization method to achieve all the benefits provided by the use of via fences, without a significant deterioration of impedance matching at the signaling microstrip lines. The proposed method exploits our recent formulation for developing surrogate models using polynomial-based functional interpolants [5]. We start from a zero-order model that is as simple as a fixed EM model response. This zero-order model is enhanced by multidimensional polynomial interpolants around a reference base point in the design space. The polynomial approximation is a low-order function of the design variables, and it is used to interpolate highly accurate EM responses in a region of interest around the selected base point. Globally optimal values for the surrogate model weighting factors are efficiently calculated in closed form. By optimizing the surrogate model response, we efficiently find an optimal performance for the EM model of the microstrip lines with via fences. II. MICROSTRIP TRACES WITH VIA FENCES A couple of parallel microstrip traces with an intermediate via fence is illustrated in Fig. 1. The structure uses an FR4 dielectric with a relative dielectric constant ε r = 4.4 and a loss tangent tan δ = 0.02 at 10GHz. The substrate height is H = 1.575 mm. The spacing between the microtrip lines and the via fence is S = 0.75 mm. Via fence has a width W vf = 2 mm, Fig. 1. Microstrip traces with via fence (W is optimized to improve impedance matching). 978-1-4244-6867-6/10/$26.00 ©2010 IEEE 125