3424 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 9, SEPTEMBER 2016 Process Options Impact on ESD Diode Performance in Bulk FinFET Technology Shih-Hung Chen, Member, IEEE, Geert Hellings, Steven Thijs, Dimitri Linten, Senior Member, IEEE, and Guido Groeseneken, Fellow, IEEE Abstract—Bulk FinFET is the main technology option for sub-20-nm CMOS nodes. However, newly introduced process options in advanced bulk FinFET technologies can result in significant deterioration of intrinsic electrostatic discharge (ESD) performance. In this paper, the impact on ESD performance induced by the process options beyond 20-nm nodes is explored on the ESD protection diodes. Index Terms— Electrostatic discharge (ESD), ESD protection diodes, FinFET, landing pad (LP). I. I NTRODUCTION A S CMOS FETs shrink from 32 to 22 nm or beyond, the need for short-channel effect control and the increase of driving current have forced CMOS device technologies to move from “planar” to “FinFET” device architecture [1], [2]. Silicon-on-insulator (SOI) FinFET, which is only a thin Si film built on a buried oxide layer, was first proposed and it has demonstrated excellent transistor I –V characteristics. Unfor- tunately, the buried oxide layer in SOI FinFET deteriorates thermal dissipation and device reliability [1]–[3]. A second type of FinFET technology without buried oxide layer is bulk FinFET [3]–[5]. Here, fin structures are fabricated on a bulk Si substrate and the fins are directly connected to Si substrate, as shown in Fig. 1. This does not only improve the thermal dissipation and the device reliability [3]–[6], but also reduces manufacturing cost. Recently, the bulk FinFET technology has been implemented in commercial CPU IC chips [7]. Since 2009, electrostatic discharge (ESD) characteristics of bulk FinFET have been investigated. The ESD-related com- parisons between SOI and bulk FinFET have been shown in the prior works [6], [8]. However, the bulk FinFETs used in these prior works were based on 45 (or 32 nm) technology node, which is a hybrid architecture between planar and fin. The fin width can be varied from several tens of nanometers to hundreds of micrometers. In this paper [9], the ESD characterization of bulk-FinFET technology with a layout compatible with the sub-20-nm generation nodes is presented. In Section II, the specific process changes toward sub-20-nm Manuscript received April 11, 2016; revised July 11, 2016; accepted July 20, 2016. Date of current version August 19, 2016 S.-H. Chen, G. Hellings, S. Thijs, and D. Linten are with imec, Leuven B-3001, Belgium (e-mail: shih-hung.chen@imec.be). G. Groeseneken is with imec, Leuven B-3001, Belgium, and also with the Electrical Engineering Department, Katholieke Universiteit Leuven, Leuven B-3001, Belgium (e-mail: guido.groeseneken@imec.be). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2016.2597000 Fig. 1. Illustrated cross-sectional views of (a) SOI FinFET and (b) bulk FinFET. nodes are together with its impact on ESD protection. The experiments and the measurement results are described in Sections III and IV. More detailed discussion and TCAD device simulation are included in Section V to further explain the observed effects. This paper is concluded in Section VI. II. I MPACT OF PROCESS OPTIONS TOWARD THE NEXT GENERATION When research of bulk FinFET technology moved into sub- 20-nm nodes, several process features have been modified in order to further shrink the transistor footprint and rein- force its characteristics during normal operation. For example, the lithography process with self-align double patterning technique [10] and the epitaxial growth of source and drain (S/D) [11] are the most significant changes. However, the impact of these advanced processes on ESD characteristics is still remained to be studied. First, due to the double pattern- ing technique, the fin width would be fixed, approaching 10 nm in sub-20-nm FinFET technology. Fin widths have been proven as an essential parameter of ESD characteristics [6]. According to [8], wide fin devices are more suitable than narrow fin devices for ESD protection. Unfortunately, wide fin devices might not be available in these advanced FinFET technologies. Second, because of the fixed narrow fins and epitaxially grown S/D, there will be no wide diffusion area, also named landing pad (LP), for the contact plugs (or strips) landing, which connects directly with the bulk. Instead, all narrow fins are connected together by the epitaxially grown S/D, as shown in, and these S/D areas are now only connected to the substrate bulk through the narrow fin structures. Consequently, all ESD currents have to discharge through the small cross-sectional area of these narrow fin structures. 0018-9383 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.