Analysis and Minimization of Short-Circuit Current in Mesh Clock Network Seongbo Shim, Minyoung Mo, Sangmin Kim, and Youngsoo Shin Department of Electrical Engineering, KAIST Daejeon 305-701, Korea Email: sbshim@dtlab.kaist.ac.kr Abstract— Mesh clock network is very effective at reducing clock skew. But mesh causes a large increase of power consump- tion, in particular due to shorted buffers. We first analyze the short-circuit power consumption of the mesh clock network. It is observed that skew distribution of premesh tree is important in determining the amount of short-circuit power. We then propose a new clock buffer, which practically eliminates short-circuit current in a mesh network. Experiments on a few test circuits using 40-nm technology indicate that clock power consumption is reduced by 13.0% on average with 4.8% of area increase; this can be compared to buffer sizing, which only achieves 5.6% saving of power. I. I NTRODUCTION Tree and mesh are two popular structures of clock distribu- tion network. Tree is more commonly used in ASIC design. It is however very susceptible to on-chip process variations [1], which leads to large amount of clock skew. Mesh has been widely used in high performance processor designs [2] for smaller skew. Its structure is illustrated in Fig. 1. Clock sinks, such as flip-flops, are driven by postmesh buffers to ensure proper amount of clock transition time; postmesh buffers are then connected to mesh through stubs; a premesh tree then connects a clock source to mesh. A spine structure may be used instead of mesh [3]. A tree may be modified to reduce skew by shorting some buffers [4], which shares the same motivation of mesh. Clock distribution network consumes large amount of power, e.g. 40% of total power in microprocessors [5]. Power consumption is even more important in mesh due to substantial use of wires. A component of power that draws a particular attention is short-circuit current. This can easily be understood by referring to Fig. 2, which shows two leaf-stage clock buffers (LCBs) of premesh tree connected to mesh. If clock falls earlier in one LCB, a path of short-circuit current establishes as indicated in Fig. 2. The period of time the two LCBs are shorted is determined by skew of premesh tree. One method to reduce short-circuit current is buffer siz- ing [6]. In Fig. 3(a), if clock arrives later at the first LCB (than at the second) and earlier at the third, buffer sizing is performed at the two LCBs so that short-circuit current is reduced. The extent of sizing is determined by how much clock arrives later or earlier. The extra capacitor may be added to compensate for the decreased buffer capacitance, so that the load of buffers driving LCBs remains unchanged. Clock source Postmesh tree Premesh tree LCB Mesh FFs Postmesh buffer Stub Fig. 1. Structure of mesh clock network. Another method, named high impedance buffer (Hi-Z buffer) [7], is illustrated in Fig. 3 (b). Two extra buffers are inserted before pMOS and nMOS transistors; the buffer in front of pMOS is fast when 1 is propagated but slow for propagating 0; the opposite is true in the buffer in front of nMOS. It is easy to see that the period when both pMOS and nMOS are turned off is extended both for rising and falling input, which helps reduce short-circuit current. Our main contributions in this paper are as follows. • Analysis of short-circuit current of mesh clock network (Section II.A and II.B), which indicates that short-circuit current increases as the standard deviation of premesh skew increases. • A new clock buffer, which practically eliminates short- circuit current, and its assessment (Section III); clock power consumption decreases by 13.0% on average of 10 test circuits with 4.8% of area overhead. II. ANALYSIS OF SHORT-CIRCUIT CURRENT Two test circuits from open cores [8], ac97 ctrl and usb funct, were taken for the experiment. Each circuit was syn- thesized and placed using 40-nm industrial library. Postmesh 978-1-4799-2987-0/13/$31.00 ©2013 IEEE 459