VIPER: A V ersatile and I ntuitive P attern GenER ator for Early Design Space Exploration Gaurav Rajavendra Reddy, Mohammad-Mahdi Bidmeshki and Yiorgos Makris gaurav.reddy@utdallas.edu, bidmeshki@utdallas.edu, yiorgos.makris@utdallas.edu Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX 75080, USA Abstract—Contemporary technology nodes exhibit high defec- tivity due to complex interactions between the process and certain layout topologies/patterns. Foundries identify such patterns dur- ing diagnosis, Scanning Electron Microscope (SEM) inspections, Failure Analysis (FA), etc., and create a database to restrict their presence in future designs. However, such a database can be generated only after fabricating a few products, hence making this process reactive. Ideally, foundries would prefer to have a proactive approach, where such sensitive patterns are available up-front during technology development. Thereby, they can build accurate Hotspot Detection models and offer a robust Product Design Kit (PDK) to even the earliest of customers, either by en- suring that the process is immune to such patterns or by including them in the Design For Manufacturability Guidelines (DFMGs). To enable this, Early Design Space Exploration (EDSE) can be performed, wherein an Electronic Design Automation (EDA) tool generates synthetic layout patterns. In this work, we introduce VIPER, a novel, controlled random walk-based pattern genera- tion method, which not only generates realistic and Design Rule- clean layout patterns, but which also offers versatility so that the generated patterns can be intuitively customized to specific needs. To ensure that the generated patterns are representative of real designs, we data mine designs in previous technology nodes and we learn some of their typical characteristics. Effectiveness of the proposed method is contrasted against the state-of-the-art, commercially available EDA tool. I. I NTRODUCTION Lithography is an extremely complex task and one of the major challenges during technology development in advanced process nodes. Construction of Optical Proximity Correction (OPC) keywords and lithography recipes begins in the early stages of technology development when only basic Design Rules (DRs) are defined and very little, if any, real layout content is available [1]. Therefore, during this process, lithog- raphers must depend on traditional test structures and/or layout examples from previous technology nodes. As a result, the process/recipe is exposed to and optimized for only a small set of patterns among a vast array of options in the design space. When the technology goes into production and large scale designs are fabricated, however, the process is exposed to many new patterns which were never seen during the development phase. Interestingly, as shown in [2], [3], such previously unseen patterns continue to appear as more designs are fabricated throughout the lifetime of a process. Inevitably, this results in high systematic defectivity, as the process is not optimized for all patterns found in real designs. Unfortunately, once the process is in production, root cause analysis of all pattern-related defects and correction through process changes becomes expensive, time-consuming and, often, intractable. Therefore, common practice is to categorize defect-causing patterns as risky/hard-to-manufacture and restrict their use in future designs. As an alternative, Early Design Space Exploration (EDSE) can be performed. In EDSE, a large number of synthetic patterns which resemble real layouts is generated up-front during technology development, using only the basic DRs [4]. A database of such patterns enables the foundry to develop a more robust technology node by: (i) using layout-like patterns during lithography recipe development and ensuring that the process is amenable to a large variety of patterns [1], (ii) designing and characterizing pattern-based test structures on silicon [5], (iii) formulating Pattern Matching (PM) rules or Design For Manufacturability Guidelines (DFMGs) around high-risk patterns and offering a robust Product Design Kit (PDK) to even the earliest of customers, and (iv) performing lithographic simulations on a large dataset and building ac- curate hotspot detection models to identify sensitive patterns in future designs [6], [7]. For EDSE to be effective, how- ever, the synthetic layout pattern generation method and tool should exhibit several key attributes: First and foremost, it should be able to generate a wide variety of random patterns which explore and accurately reflect the entire design space. Second, resulting patterns should obey DRs and resemble real Integrated Circuit (IC) layout snippets. Third, it should enable the user to intuitively control various aspects of the generated patterns and accommodate specific needs, such as generation of constrained pattern types or patterns from certain design corners. To the best of our knowledge, the State-Of-The-Art (SOTA) in this area is a commercially available Electronic Design Automation (EDA) tool (i.e., Mentor’s Layout Schema Gen- erator (LSG)), the use of which for synthetic layout pattern generation is described in [4]. This tool uses a set of ‘unit patterns’ and randomly places them on a grid of certain size, seeking to produce a realistic design. Some operating modes of this tool are fully automated or require minimal human involvement. In such cases, however, the produced patterns tend to be rather unrealistic and of limited utility to the EDSE process. Other modes, requiring significant amount of human effort, produce very realistic and DR-clean patterns. Nevertheless, despite using best modes, settings and practices, as prescribed by the tool vendor, it tends to generate patterns which only cover a limited portion of the design space, leaving Paper 11.3 978-1-7281-4823-6/19/$31.00 c 2019 IEEE INTERNATIONAL TEST CONFERENCE 1 Authorized licensed use limited to: Univ of Texas at Dallas. Downloaded on August 02,2020 at 22:20:47 UTC from IEEE Xplore. Restrictions apply.