8 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, NO. 1, JANUARY 2018 A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS Harish K. Krishnamurthy , Member, IEEE, Vaibhav Vaidya, Member, IEEE, Pavan Kumar, Member, IEEE, Rinkle Jain, Member, IEEE, Sheldon Weng, Member, IEEE, Stephen T. Kim, George E. Matthew, Member, IEEE, Nachiket Desai, Member, IEEE, Xiaosen Liu, Member, IEEE, Krishnan Ravichandran, Member, IEEE, James W. Tschanz, Member, IEEE, and Vivek De, Member, IEEE Abstract—A fully integrated digitally controlled two-phase buck voltage regulator (VR) with on-die solenoid inductors with a planar magnetic core is demonstrated in 14-nm tri-gate CMOS for fine-grained power delivery/management domains of high power density in system-on-chips while enabling ultra-thin (z-height) packages. The VR achieves 1-A/mm 2 power density for 400-mA load current with a measured peak efficiency of 84% at 100-MHz switching frequency including a digital PWM with >9 bits (8 ps) of resolution. Index Terms—Buck converter, DPWM, dual edge modulation DPWM, fully integrated voltage regulator, high frequency, high resolution digital controller, on-die solenoid inductor, planar magnetic core. I. I NTRODUCTION F ULLY integrated voltage regulators (IVRs) promise effi- cient and wide-range local power delivery and manage- ment capability with fast transient response for fine-grain dynamic voltage and frequency scaling (DVFS) domains of high power density in complex system-on-chips (SoCs). The tradeoff between having a platform regulator versus an on- die regulator to achieve best power savings is workload and application dependent. Furthermore the choice of on-die regulators be it switching or linear regulators could also be application specific. For example, a combination of external switching regulators and on-die linear regulators with bypass was reported in [1]. Higher dropout voltages result in lower overall efficiency but [1] reports overall power savings due to DVFS despite the low drop out losses. Fully on-die buck-based switching regulators (VRs) provide higher overall efficiency and power density across a wide range of voltages and currents. However, integration of high-quality power inductors Manuscript received May 07, 2017; revised August 08, 2017; accepted September 18, 2017. Date of publication October 25, 2017; date of current version December 26, 2017. This paper was approved by Guest Editor Keith Bowman. This work was supported by the Defense Advanced Research Projects Agency (DARPA). (Corresponding author: Harish K. Krishnamurthy.) The authors are with the Circuit Research Lab, Intel Corporation, Hillsboro, OR 97124 USA (e-mail: harish.k.krishnamurthy@intel.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2017.2759117 that can support high current density with minimal losses is a major challenge. Integrated buck VR designs with different types of power inductor integration technologies have been reported [2]–[4]. Fig. 1 shows a pictorial representation of the inductor state of the art and their relative co-location with the load die. In [2], planar lateral coupled power inductors with non- planar magnetic cores for higher inductance, quality factor, and current density, are integrated on a separate silicon inter- poser die which is then wire-bonded to the VR die on a common ball grid array laminate. While an interposer die for inductor integration enables small inductor footprint, par- asitic impedances of the wire-bonds degrade inductor quality, overall VR performance, and efficiency. In addition, the total thickness (z -height) of the packaged two-die stack is too large for ultra-thin form factor systems. High quality-factor air-core power inductors are integrated within the package layers in [3], utilizing the thick package core. However, they are difficult to integrate in ultra-thin coreless packages with few package lay- ers. Also, scalability of the inductor footprint to fine domains is limited. Furthermore, since the inductors cannot be co- located with the SoC DVFS domains for both of these inductor options, scalability to finer domains is curtailed. Planar lateral spiral inductors without magnetics are integrated directly on the VR die in [4], utilizing upper metal layers. Although this option is suitable for realizing ultra-thin packaged dies and the inductor footprint can be scaled to finer domains, the quality factor and inductance density are too low to support high current density needed for viable on-die power conversion. In this paper, we demonstrate a fully integrated digitally controlled two-phase high frequency buck VR with on-die solenoid power inductors with multiple vertical windings around a high-permeability planar magnetic core, utilizing two thick-top metal layers, implemented in 14-nm tri-gate CMOS (Fig. 2). This inductor structure and on-die integration technology enable lower losses and higher current density than the on-die planar lateral spiral inductor without magnetics [4]. At the same time, it offers: 1) superior scalability of inductor footprint; 2) finer DVFS domains via inductor co- location with the domain; and 3) easier realization of ultra-thin 0018-9200 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.