SPS – UNICAMP 2014 ARCHICTECTURE OF FPGA-BASED CONTROL OF A STATIC POWER BUCK CONVERTER ARCHITECTURE OF A FPGA-BASED CONTROL OF A STATIC POWER BUCK CONVERTER Yuzo Iano, Leandro Lima FEEC DECOM Universidade Estadual de Campinas (Unicamp) yuzo@decom.fee.unicamp.br, lblima@decom.fee.unicamp.br Abstract – A methodology for the development of a digital controller for a static power converter is presented in this paper, including the behavioral model of the analog part of it. The digital controller is realized using hardware description language VHDL on FPGA, and the analog part is modeled using the Matlab Simulink. The integration of the whole structure – converter and control system - allows that the control system may be simulated, tested and validated with no need of a prototype. Keywords: FPGA, VHDL, Simulink, Functional Verification 1. Introduction This work shows the design of a digital controller for an "SPC" using the hardware description language VHDL on FPGA, and it interaction with the analog model made on Simulink. We will be presenting all the architecture and the digital blocks used during design on FPGA. A top level diagram block of the whole structure is presented, shown on Figure 1. Figure 1. Static Power Converter Diagram Due to an implementation decision this work was performed in 3 (three) parts: the first part is the architecture and design of the digital controller on FPGA, the second part represents the interface between FPGA and Simulink, and the third part represents the modelling of the static power converter with Simulink. 2. FPGA Digital Controller The FPGA adopted was the Xillinx Spartan 3E- 500, which contains 500K system gates and 10.476 equivalent logic cells, what is more than enough for this work purpose. 2.1. Sub-Blocks Depending from the signal received from serial interface, the digital controller block generates a signal to the analog part, and keeps it signal as stable as possible using a PID, the figure below was extracted from a schematic design that illustrates the PID control and PWM has on the system, shown on Figure. 2. Figure 2. Schematic of Control Power Converter. The ADC converter sends its output to the adder, and this device does a comparison between the serial input and the ADC output. The comparison result is sent to PID, in order to generate a correct duty-cycle to keep the output voltage in the required operation range, using for achieve this PWM. The Digital Control block, implemented using FPGA, is based on three blocks: configurable logic blocks (CLB), Input Output blocks (IOB) and interconnection switches. These blocks are, usually, made using NOR and NAND logic ports. The Digital Controller was developed using VHDL – VHSIC Hardware Description Language. Using this language, it is possible to