MAXIMUM LIKELIHOOD CARRIER PHASE SYNCHRONIZATION IN FPGA-BASED SOFTWARE DEFINED RADIOS Michael Rice Brigham Young University Provo, Utah Chris Dick Xilinx, Inc. San Jose, California fred harris, Signal Processing Chair San Diego State University San Diego, California ABSTRACT Digital signal processing techniques are applied to maximum likelihood carrier phase synchronization for QPSK and QAM in an all-digital sampled data receiver. To achieve the flexibil- ity required by modern Software Defined Radios (SDR’s), this task must either be performed in a DSP processor (reconfigura- ble software) or in an FPGA (reconfigurable hardware). This paper describes the design process for an FPGA-based design and summarizes the FPGA resources required for QPSK carrier phase synchronization. 1. INTRODUCTION The last two-decades has borne witness to a steady trend of migrating many radio functions, traditionally performed by analog processing tasks, to DSP based implementations. In conjunction with this DSP insertion, we have seen the boundary between the analog and digital segments in the signal conditioning chain move inexorably towards the antenna. The implementation of these high-performance digital communica- tion systems has been made possible by advances in semiconductor process technology in the form of application specific standard parts (ASSPs), full custom silicon chips, instruction set based digital signal processors (DSPs) and high performance general-purpose processors (GPP). In current generation systems, the hardware solution is often best provided using a heterogeneous computing approach, using the silicon appropriate to each particular function. In the early 1990's field programmable gate arrays (FPGAs) also played a role in digital communication hardware where they were often applied as glue logic to support bus interfacing, complex state machines and memory controller tasks. In recent years, FPGA technology has undergone revolutionary changes. Gate densities and clock speeds of recent generation FPGAs provide the communication system architect with a highly configurable logic fabric that can be used for realizing sophisticated real- time signal processing functions. The ever-increasing demand for mobile and portable com- munication forces two competing requirements on system de- sign: 1) the requirement for high-performance systems em- ploying advanced signal processing techniques to allow operation with very small implementation losses, and 2) the requirement to respond to market and fiscal pressures to easily accommodate evolving and fluid standards. Software defined radios (SDRs) are emerging as a viable solution for meeting the conflicting demands in this arena. SDRs support multimode and multi-band modes of operation and allow service providers an economic means of future-proofing these increasingly complex and costly systems. One of the challenging tasks in a communication system is carrier and symbol timing recovery. A large amount of time is spent solving these problems, and frequently a large amount of hardware and software in a SDR is dedicated to synchronization [1,2]. This paper examines techniques for developing, modeling and generating FPGA implementations of carrier synchronization loops for QPSK and QAM modulations. 2. CARRIER RECOVERY IN AN SDR The basic operations required by an all digital QPSK or QAM receiver are illustrated in Figure 1. QPSK and QAM signals carrier information on the amplitudes of the quadrature carriers. The quadrature down-conversion and matched filter operations produce estimates of the quadrature amplitudes which are the basis of the data decisions. The role of carrier phase synchronization is to perform the quadrature down-conversion using phase coherent replicas of the quadrature carriers. ADC DDS FIR LPF FIR LPF FIR LPF FIR LPF down sample matched filter detect data ( ) φ θ ˆ sin 0 + - n ( ) φ θ ˆ cos 0 + n ) (t r ) (n r Fig. 1. Block diagram of basic QPSK/QAM digital receiver. There are many options for implementing carrier phase and frequency synchronization in a digital communication system. At the heart of all synchronizers is the phase-locked loop (PLL). An all-digital receiver can be implemented with a digital phase-locked loop (DPLL) as shown in Figure 2. This DPLL employs a proportional plus integral loop filter formed by a scaled digital integrator and a scaled direct path. The filter coefficients K P and K I control the PLL bandwidth and damping factor. In the digital implementation, the VCO takes the form of a direct digital synthe- sizer (DDS). The phase detector is implemented using the arctangent operation suggested by the ATAN block. The most complex component in the loop is the phase detector. Since the phase of QPSK or QAM signals is data dependent, the phase detector must strip the modulation from the received signal and produce a signal proportional to the phase difference between the local generated quadrature carriers and those of the received signal. The complexity of the phase detector can be reduced by computing a signal proportional to the sine of the phase difference φ φ φ ˆ - = ∆ . Note that sin(∆φ) is monotonic with ∆φ for –π/2 ≤ ∆φ ≤ π/2 and is a good phase estimator in that interval. The periodicity of the sine function produces the π/2 phase ambiguity associated with the phase detector. For small ∆φ, sin(∆φ) ≈ ∆φ so that the sine function approximates the ideal phase detector for small ∆φ. The reduced complexity phase detector for QPSK is illustrated in Figure 3. The phase error is computed by comparing the phase