1948 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004 A 20-W Stereo Class-D Audio Output Power Stage in 0.6- m BCDMOS Technology Paul Morrow, Member, IEEE, Eric Gaalaas, Member, IEEE, and Oliver McCarthy Abstract—This paper presents a highly power efficient 2 20-W class-D audio output power stage implemented in 0.6- m BCDMOS technology. The presented power stage is capable of driving 2 8- loads from a 20-V power supply at a power efficiency approaching 90%. Circuit details of thermal detection, over-current protection, and startup speaker click/pop are also presented. The performance of open-loop Class-D output stages are limited by the distortion mechanisms present within the power stage itself. A third-order PWM modulator was prototyped and used to dramatically improve the performance of the Class-D output stage by using feedback. The results of this work are also presented. Index Terms—Class-D amplifier, dead-time, full-bridge, power amplifier, PWM. I. INTRODUCTION T HE new millennium has seen the emergence of Class-D audio amplifiers replacing traditionally used linear am- plifiers, such as Class-AB, in the commercial audio amplifier arena. Class-D has come to the forefront in audio amplification due to a number of reasons: 1) The high power efficiency renders the use of heat sinks unnecessary. 2) The development of the BCDMOS process allows the combination of high-voltage low- switches with stan- dard low-voltage 5-V devices enabling a low cost mono- lithic solution. 3) The advances in sigma-delta modulator technology can be readily employed in Class-D amplifiers, enabling Class-D to achieve audio performance levels rivaling and even sur- passing their linear counterparts [1]. The goal of this design was to produce a 20-W stereo Class-D monolithic output stage capable of driving two 8- loads without the requirement for an external heat sink. The specification for the output stage required that the design func- tion robustly over a supply voltage ranging from 8 to 20 V. It was also necessary to provide support circuitry for the output stage such as over-temperature, over-current, and speaker pop/click reduction circuitry that could also function robustly over the 8–20-V supply range. The majority of Class-D output power stages require several passive components in order to provide a bootstrapped supply Manuscript received October 21, 2003; revised June 1, 2004. P. Morrow is with Analog Devices, Raheen Industrial Estate, Limerick, Ire- land (e-mail: Paul.Morrow@analog.com). E. Gaalaas is with Analog Devices, Wilmington, MA 01887 USA. O. McCarthy is with the Department of Electronic and Computer Engi- neering, University of Limerick, Limerick, Ireland. Digital Object Identifier 10.1109/JSSC.2004.835820 Fig. 1. Cross section of an nDMOS device. voltage for the high-side switch in the output stage. An addi- tional goal of this design was to eliminate the necessity of ex- ternal passive components for bootstrapping in order to reduce package pin count and external component count. The motiva- tion for reducing external component count was to lower system cost. An alternative high-side gate-drive drive scheme would therefore be required to accommodate removal of bootstrapping components. The outline of this paper is as follows. Section II discusses the reasons for choosing the BCDMOS process for this design. Sec- tion III illustrates the gate-drive control scheme along with a de- tailed description of the gate-drive circuits. Section IV discusses the support circuitry necessary for the output stage. Sections V and VI present experimental results and some final conclusions. II. BCDMOS PROCESS,OPTIMIZED FOR CLASS D The Class-D output stage is realized in a 0.6- m double-poly triple-metal Bipolar, CMOS, DMOS (BCDMOS) technology. Fig. 1 shows a cross section of an nDMOS device. The main features of a DMOS device are as follows: • It is a (lateral) double-diffused MOS transistor. • The device is asymmetrical. • A lightly doped Nwell (extended drain) region supports high drain voltages (most of is dropped in silicon). • The thin gate oxide allows a high device but restricts . • The Pbody is shorted to source of device in metal 1. The attractive features of the BCDMOS process suitable for Class D technology include: 1) DMOS devices facilitate power supply voltages up to 30-V operation. DMOS transistors allow relatively high 0018-9200/04$20.00 © 2004 IEEE