Low-Cost TSH (Through-Silicon Hole) Interposers for 3D IC Integration John H. Lau, Ching-Kuan Lee, Chau-Jie Zhan, Sheng-Tsai Wu, Yu-Lin Chao, Ming-Ji Dai, Ra-Min Tain, Heng-Chieh Chien, Chun-Hsien Chien, Ren-Shin Cheng, Yu-Wei Huang, Yuan-Chang Lee, Zhi-Cheng Hsiao, Wen-Li Tsai, Pai-Cheng Chang, Huan-Chun Fu, Yu-Mei Cheng, Li-Ling Liao, Wei-Chung Lo, and Ming-Jer Kao Electronic and Optoelectronic Research Lab, Industrial Technology Research Institute Rm.168, Bldg.14, No.195, Sec. 4, Chung Hsing Road Chutung, Hsinchu 310, Taiwan 886-3591-3390; johnlau@itri.org.tw ABSTRACT In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top-chip, bottom-chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be preformed to demonstrate the integrity of the SiP structure. INTRODUCTION One of the applications of 3D IC integration is passive interposer or called 2.5D IC integration [1-3]. In general, it consists of a piece of device-less silicon with TSVs (through- silicon vias), RDLs (re-distribution layers), and/or IPDs (integrated passive devices) supporting one or more high- performance, high-density, and fine-pitch chips without TSVs [4-12]. This is schematically shown in the top drawing of Figure 1. It can be seen that the TSV/RDL interposer is supporting Chip-1 and Chip-2 side-by-side on its top surface. Another design is shown in the bottom drawing of Figure 1. It can be seen that the interposer is supporting these two chips on its top- and bottom-side. In this case, the size of the interposer can be smaller (or more chips can be placed on the same size of interposer), and the electrical performance can be better because the chip-to-chip interconnects are face-to-face instead of side-to-side [13-22]. Also, it is truly a 3D IC integration with a passive interposer, which will be the focus of this study. TSV/RDL Interposer 3D IC Integration with Passive Interposer 2.5D IC Integration with Passive Interposer Micro Bump TSV Micro Bump TSV TSV/RDL Interposer Chip-2 Chip-1 Chip-1 Chip-2 Advantages:  Smaller size of interposer (or same size of interposer supporting more chips)  Better electrical performance (face-to- face interconnects instead of side-by-side  3D IC integration Fig. 1 3D IC integration with a passive interposer. Organic Package Substrate Solder bump RDL RDL RDL RDL RDL Cu wire or pillar Micro Solder joints RDL chip Through-Si Holes (TSH) Interposer Non-metallization holes on the TSH interposer chip chip chip Solder bump Solder ball Solder ball Printed Circuit Board Not-to-Scale Underfill is needed between the TSH interposer and package substrate. Underfill may be needed between the TSH interposer and chips. Fig. 2 A SiP which consists of a TSH interposer supporting chips with Cu pillars on its top-side and chips with solder bumps on its bottom-side. TSV is the heart and most important key enabling technology of 3D IC integration. Usually, there are six key steps in making a TSV, namely: (a) via formation by either deep reactive ion etch (DRIE) or laser drilling, (b) dielectric layer by plasma-enhance chemical vapor deposition (PECVD), (c) barrier and seed layers by physical vapor deposition, (d) via Cu-filling by electroplating, (e) chemical- mechanical polishing (CMP) to remove the overburden Cu, and (f) TSV Cu reveal by backgrinding, Si dry-etching, low- temperature passivation, and CMP. Thus, how to make low- cost TSVs is one of the important research topics for 3D IC integration. In this study, a class of very low-cost interposer with through-silicon holes (TSHs) and with chips on its both sides (a real 3D IC integration) is developed. Figure 2 schematically shows a SiP with a TSH interposer supporting a few chips on its top- and bottom-side. The key feature of TSH interposers is there is not metallization in the holes and the dielectric layer, barrier and seed layers, via filling, CMP for removing overburden copper, and Cu revealing are not necessary. Comparing to the TSV interposers, TSH interposers only need to make holes (by either laser or DRIE) on a piece of silicon wafer. Just like the TSV interposers, RDLs are needed by the TSH interposers. The TSH interposers can be used to support the chips on its top side as well as bottom side. The holes can let the signals of the chips on the bottom-side transmit to the chip on the top-side (or vice versa) through the Cu pillars and solders. The chips on the same side can communicate to each other with the RDLs of the TSH interposer. Physically, the top chips and bottom chips are connected through Cu pillars and micro solder joints. Also, the peripherals of all the chips are 978-1-4799-2407-3/14/$31.00 ©2014 IEEE 290 2014 Electronic Components & Technology Conference Authorized licensed use limited to: Industrial Technology Research Institute. Downloaded on April 12,2023 at 09:49:14 UTC from IEEE Xplore. Restrictions apply.