Fast Real-Time LIDAR Processing on FPGAs K. Shih, A. Balachandran, K. Nagarajan, B. Holland, C. Slatton, A. George NSF Center for High-Performance Reconfigurable Computing (CHREC) Department of Electrical and Computer Engineering University of Florida, Gainesville, FL Abstract—Light Detection and Ranging (LIDAR) plays an important role in remote sensing because of its ability to provide high-resolution measurements of 3D structure. For time-sensitive airborne missions, fast onboard processing of LIDAR data is desired and yet difficult to achieve with traditional embedded CPU solutions due to the computational requirements. FPGAs have the potential to speed up processing by employing multi-level parallelism, but their use in LIDAR processing has typically been limited to data capture due to the difficulties associated with efficiently migrating LIDAR processing algorithms to FPGAs. We demonstrate two equivalent FPGA designs for coordinate calculation of LIDAR data written using different languages (VHDL and MATLAB-based AccelDSP), comparing their performance and productivity. For the VHDL design, a ~14× speedup is obtained over an Opteron processor on a Cray XD1 system. In addition, a recently proposed performance prediction methodology is employed, and the accuracy of its pre-implementation predictions is analyzed. 1. Introduction Over the past few decades, airborne LIDAR technology has emerged as an important remote sensing modality for many scientific and military applications [1], [2]. Most LIDAR applications involve terrain mapping, but LIDAR data have also been fused with other sensor types, such as multi-spectral imagery [3]. The importance given to LIDAR data comes from its capabilities to provide high-resolution position information on targets of interest from a remote distance. These targets include terrain topography, vegetation structure, and building features. Obtaining high-resolution data is made possible through high density of laser returns. For example, Optech Gemini system records laser returns at frequencies as high as 167 kHz [1], [2], [4], collecting more than ten million laser returns every minute. Raw LIDAR data (laser ranges, scan angles, etc.) recorded by the sensor needs to be processed in order to present information in the form of a 3D point cloud, and such processing is computationally demanding at near realtime rates due to the high laser pulse rates. For example, compact modern ground-based LIDARs can record laser ranges for pulse rates up to a few kHz [5]. Discrete-return airborne LIDARs operate at laser pulse rates in excess of 150 kHz and record four or more returns per transmitted pulse [2]. Spaceborne LIDARs typically have lower pulse rates, but digitize the return pulse into 100 or more samples [6]. As a result, LIDAR data are often saved to onboard storage devices and processed off-line on PC workstations at a later time. However, in a time-constrained scenario, the acquired data have to be processed onboard for realtime analysis and feedback. Onboard processing of LIDAR data may be feasible if LIDAR operators on the aircraft use commercially available laptops with large-volume hard disk drives, but many General-Purpose Processors (GPPs) on laptops still render tasks serially and thus likely fail to meet the realtime analysis requirements. In contrast to GPPs, High-Performance Embedded Computing (HPEC) systems featuring FPGAs can be used to speed up the procedure by exploiting multi-level parallelism inherent in algorithms used for LIDAR processing. Moreover, the reconfigurability of FPGAs opens the possibility to migrate diverse signal processing algorithms to hardware designs according to a particular application’s requirements. Although FPGAs have much to offer in terms of power, adaptivity, and performance improvements, developing efficient designs that function at high frequencies using conventional hardware description languages (HDLs) can be unwieldy for application scientists because the underlying programming techniques commonly require detailed hardware knowledge that can be beyond their comprehension or interest. In addition, short design times and more importantly shorter re-design times would increase the productivity of application scientists when migrating complex algorithms. Therefore, generating efficient hardware designs by translating high-level languages (HLLs) to HDLs using application mappers (HLL tools) is highly desirable. It is also critical for application designs to meet the requirements of the project during the migration to hardware. Yet, different algorithmic approaches in combination with potential platform architectures can likely lead to dissimilar designs with distinct performance improvements (or degradations), and this makes it time-consuming and inefficient to determine the most favorable choice of algorithmic approach and platform architecture by developing full hardware designs. Therefore, it is important to estimate the likely outcome of a new design (speedup and resource usage) before expending significant effort on any specific algorithm, architecture, or platform. In other words, an efficient and accurate prediction methodology can likely increase performance and productivity while minimizing unnecessary development time and effort. The remainder of this paper is structured as follows. In Section 2, previous works related to LIDAR processing on FPGAs are reviewed, followed by a discussion of the fundamentals of onboard LIDAR processing in Section 3. In