Journal of Engg. Research ICAPIE Special Issue pp. 8-18 Area Efficient Diminished 2 n -1 Modulo Adder using Parallel Prefix Adder Beerendra K. Patel*and Jitendra Kanungo Department of Electronics & Communication Engineering, Jaypee University of Engineering & Technology, Guna-473226, India. *Corresponding Author: beerendrapatel23@gmail.com ABSTRACT Residue Number System has to carry free operation and its various applications like digital signal processing, multimedia, security purpose, and medical perception. Removes of the redundant logic operation require the group carry selection logic which is dependent on Parallel Prefix Adder design. Therefore the logic operation of the pre- processing unit of PPA is simplified form to save logic resources. This modified parallel prefix adder consumes less area as compared to the existing design. In this paper, we propose the parallel architecture based on a parallel prefix tree is helpful for computation at higher speed operation. The reported design consumes 24.1% more area and 26.4% more power compare to THE proposed parallel prefix adder design. The proposed PPA design using modified carry computation algorithm and reported design used diminished-1 modulo 2n+1 adder structure is presented. A presented modulo adder design using the proposed parallel prefix adder and improved carry computation used in the previously proposed design. The proposed diminished-1 modulo (2 n +1) adder design shows a 24.5% saving in area-delay-product (ADP). Keywords: Parallel Prefix adder; Computer arithmetic; Diminished-1 representation. INTRODUCTION In the field of digital computer arithmetic, the residue number system offers advantages in terms of conversion of higher arithmetic integers into a smaller arithmetic number via parallel operation. An integer is a set of residues called moduli. RNS is a highly scalable and fast technique that is suitable for high performance (R.P. Bent et al., 1982). In a portable device design, the scaling technique is the better option for low-power digital circuit design. RNS has performed carry-free operations for compact, high-speed implementation of circuits (R. Ladner et al.,1980, A. A. Hiasat,2002). RNS applications like digital image processing, widely used in medical perception, machine view, military target finding, multimedia, and security purpose requires low power consumption and high speed. RNS achieves high speed with a parallelism nature. RNS has been adopted in the design of Digital Signal Processors (DSP). Modulo 2 n +1 multiplier is widely used in a wide range of applications including random number generator which has remarkable applications in cryptographic algorithms (Kogge P.,1973). Various cryptographic systems have been studied and implemented to ensure the security of information. In the designing of a normal modulo adder, it is essential to use continual computing stages. (Patel et al.,2007) have defined implementation architecture for modulo 2 n - (2 n-2 + 1) adder. This architecture consists of a carry-computation unit. Thereby, repetitive elements of carrying computation stages are suppressed. However, the structure is the same as the carry computation unit as for 2 n - (2 n-2 + 1) modulus. In (S. Knowles 1999), authors have described various algorithms to generate the fast carry bit. Figure 1. Basic diagram of modulo (2 n +1) adder DOI:10.36909/jer.ICAPIE.15073