Proc. Second IEEE Int Caracas Conference on Devices, Circuits and Systems (ICCDCS - 2000), Cancun, Mexico (15-17 March 2000). MOSFET MODELING FOR RF CIRCUIT DESIGN Yuhua Cheng, Chih-Hung Chen*, Christian Enz, Mishel Matloubian, and M. Jamal Deen* Conexant Systems, Newport Beach, CA 92660, USA Department of Electrical and Computer Engineering, CRL 220 McMaster University, Hamilton, Ontario, Canada L8S 4K1 ABSTRACT In this paper, we discuss some important issues in MOSFET modeling for radio-frequency (RF) integrated- circuit (IC) design. We start with the introduction of the basics of RF modeling. A simple sub-circuit model is presented with comparisons of the data for both y parameter and f T characteristics. Good model accuracy is achieved against the measurements for a 0.25μm RF CMOS technology. The high frequency (HF) noise modeling issues are also discussed. A methodology to extract the channel thermal noise of MOSFETs from the HF noise measurements is presented and the concept of induced-gate noise is discussed briefly. The results of different noise modeling approaches are also given with the comparison of the measured data, with which the prediction capability of the HF noise behavior of any modeling approach can be examined. I. INTRODUCTION With the fast growth of the radio frequency (RF) wireless communications market, RF designers have begun to explore the use of CMOS in RF circuits. Accurate and efficient RF MOSFET models are required. It has been known that a device model emphasizing on the low frequency applications cannot be used directly in RF [1]. Compared with the MOSFET modeling at low frequency, compact RF models are more difficult to develop and do not exist in present commercial circuit simulators. Many microwave circuit designers’ use a table-look-up approach based on measurements. However, this approach requires a large database obtained from numerous device measurements, and becomes prohibitively complex when used to simulate highly integrated CMOS RF circuits. Recently, work has been reported to model the RF performance of submicron MOS devices [1-5]. Basically, they are all developed with the subcircuit approach by adding parasitic components to a core intrinsic MOSFET model. They have demonstrated good accuracy up to 10GHz. However, there are still a lot of issues to be studied, and some examples are now listed. (1) The added parasitic components should be physics-based and linked to process and geometry information to ensure the scalability and prediction capability of the model. (2) Simple sub-circuits are preferred to reduce the simulation time. (3) Clear and efficient parameter extraction methodologies should be developed. (4) HF behavior related to the thermal noise should be investigated. (5) Efficient models for NQS effects are required. In this paper, we discuss some issues that must be properly accounted for in modeling a MOSFET at RF, and present a simple sub-circuit MOSFET model. The model is accurate in y-parameters (up to the ½ f T frequency range) and f T characteristics in the device geometry range interested in RF IC. Further, we present a methodology to extract the channel thermal noise that is important in HF noise modeling. The simulation results of different noise modeling approaches are demonstrated with the measured data. II. MOSFET MODELING AT RF 1. Modeling of Parasitics As shown in Fig. 1, a four terminal MOSFET contains many parasitic components, such as the gate resistance R g , gate/source overlap capacitance C gso , gate/drain overlap capacitance C gdo , gate/bulk overlap capacitance C gbo , source series resistance R s , drain series resistance R d , source/bulk junction diode D sb , drain/bulk junction diode D db , and substrate resistances R sb , R db and R dsb . They will influence significantly the device performance at high frequency. trench trench trench trench S B D B RSB RDB RBDS RDS RS RD G RG DSB DDB CGSO CGDO N+ N+ P+ P+ P-SUB N- N- Fig. 1 A MOSFET schematic cross-section with the parasitic components. (a) Gate Resistance: The gate resistance consists mainly of the poly-silicon sheet resistance. The typical sheet resistance for a polysilicon gate ranges between 20-40 Ω/square, and can be reduced by a factor of 10 with a silicide process, and even more with a metal stack process. Signal delay at the gate due to the distributed transmission line effect at high frequency has been studied. A factor of 1/3 or 1/12 is introduced, depending on the layout structures of the gate connection, to account for the distributed RC effects when calculating the gate resistance at RF. This effect will become more severe as the gate width becomes wider and the operation frequency becomes higher. So multi-finger devices are used in the