Through Silicon Capacitor co-integrated with TSVs on silicon interposer O. Guiller a,⇑ , S. Joblot a , Y. Lamy b , A. Farcy a , J.F. Carpentier a , E. Defay b a STMicroelectronics, 850 rue Jean Monnet, Crolles 38926, France b CEA, LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France. article info Article history: Available online 17 December 2013 Keywords: TSC Decoupling capacitor MIM Silicon interposer 3D integration Packaging abstract In this paper the Through Silicon Capacitor (or TSC), a new type of decoupling capacitor integrated on a via bridge silicon interposer is presented. TSC is a tri-dimensional MIM capacitor that goes through the whole thickness of the interposer, developing its capacitive area vertically and whose fabrication process uses most of the step of Through Silicon Via own process. A demonstrator have been designed and fab- ricated to investigate the first process step of TSC, using a TIN/Al 2 O 3 /TiN MIM stack deposited in various TSV geometries, design and process flow are exposed. Morphological characterization has been held to define conformalities of the various deposited materials, proving their viabilities in such geometries. Electrical characterizations of capacitors have shown an increase of the capacitance density up to a factor of 6. Ó 2013 Elsevier B.V. All rights reserved. 1. Introduction The scaling down of transistor size has introduced a density gap between Large Scale Integration (LSI) chips supporting the transis- tors, and organic substrates that carry them. In the past few years silicon interposer has emerged as a solution to fill this gap. Higher interconnection densities and better thermal compatibility are al- lowed by the use of a silicon substrate, such that multiple hetero- geneous active dies can be reported on the same platform without thermal mismatch, offering numerous integration possibilities. Vertical electrical connections are carried out by the Through Sili- con Vias (TSV) from the front side of the interposer to its backside, where a looser routing density combined with bumps or Cu Pillars permits a good compatibility with the underlying organic sub- strate, usually a Ball Grid Array (BGA). A passivation at BGA level finalizes the packaging of the module, which can be reported on the printed circuit board (PCB), as represented in Fig. 1. Alongside the classical via-last and via-middle integration scheme for Through Silicon Vias (TSV), an alternative solution is being developed in the ‘‘via-bridge’’ [1] process, as it bridges the gap between via-middle and via-last technologies. This solution uses the high conformality and high temperature of the via-middle process to increase the aspect ratio (<2) of the via-last TSV up to 5, allowing to etch deeper TSV, and therefore to obtain thicker inter- poser (between 200 and 300 lm) where the classical TSV process limits its thickness to 200 lm. Such an interposer would provide a better robustness to handling and reliability test so that it could be directly reported on PCB in a Direct-Chip-Attach (DCA) process Fig. 2, freeing the package from the BGA constraint and its associ- ated costs. Beside the advantages already discussed, additional silicon space is offered by the interposer for integrated active or passive devices, such as decoupling capacitors. Those capacitors are part of the power delivery network (PDN) of the system; they are local energy storages that limit voltage peaks and ensure power integ- rity. Decoupling performances are driven by total capacitance va- lue and impedance of the device defines the decoupling frequency range (through its equivalent series resistance (ESR) and inductance (ESL)) [2]. Two kinds of decoupling capacitors stand out: the surface mounted devices (SMD), and embedded capacitors [3,4]. Since PDN decoupling is needed on the overall fre- quency range, capacitors are present in every floor of the package, as shown in Fig. 3: front-end plane (C FE ), back end of line (C MIM ), BGA (C BGA ) and PCB (C PCB ) varying the interconnection length, therefore ESR and ESL. Several types of capacitors are being inves- tigated for integration on silicon [5,6], and on Si-interposer as well, either planar Metal–Insulator–Metal (MIM) [7] or trench [8]; they all provide an additional decoupling stage to the LSI PDN, thus low- ering PDN impedance over a wide frequency range and decoupling intermediate frequencies [9]. In this paper, the Through Silicon Capacitor (TSC) is presented as an alternative solution for the integration of decoupling capaci- tors on a via-bridge Si-interposer. 2. Through Silicon Capacitor TSC is a 3D Metal–Insulator–Metal (MIM) capacitor which has the particularity to go through the whole thickness of the 0167-9317/$ - see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mee.2013.12.017 ⇑ Corresponding author. Address: DCOS/S3D/LP3D, CEA, LETI, Minatec, 17 rue des martyrs, Grenoble 38054, France. Tel.: +33 438785042. E-mail address: olivier.guiller@cea.fr (O. Guiller). Microelectronic Engineering 120 (2014) 121–126 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee