ICSE2006 Proc, 2006, Kuala Lumpur, Malaysia. Characterization of Strained Silicon MOSFET Using Semiconductor TCAD Tools Wong Yah Jin, Ismail Saad and Razali Ismail Faculty of Electrical Engineering, Universiti of Teknologi Malaysia, 81300 Skudai, Johor, Malaysia. Email: helommi(igmalxom ismail s(ums.edu.myand razal(i0<e.utm.mY Abstract - The paper is looking into the enhancement of conventional PMOS by incorporating a strained silicon within the channel and bulk of semiconductor. A detailed 2D process simulation of Strained Silicon PMOS (SSPMos) and its electrical characterization was done using TCAD tool [1]. With the oxide thickness, Tox of 16nm and Germanium concentration of 35%, the threshold voltage Vt for the strained Si and conventional PMOS is -0.5067V and -0.9290V respectively. This indicates that the strained silicon had lower power consumption. Beside that, the drain induced barrier lowering (DIBL) value for the strained PMOS is 0.3034V and the conventional PMOS is 0.4747V, which shows a better performance for strained silicon as compared to conventional PMOS. In addition, the output characteristics were also obtained for SSPMos which showed an improvement of Drain current compared with conventional PMOS. I. INTRODUCTION Scaling down of MOSFET devices has been the driving force in IC industry in order to achieve higher speed and lower power requirements [2]. The recent MOSFET devices have been scaled down to 50nm gate lengths where the gate oxide thickness has become thin enough to suppress the short channel effect (SCE) [3]. However further scaling down of the MOSFET beyond 50nm will cause the SCE to intensify, thus degrading the current drivability and electron mobility of a MOSFET [4]. The continuous downsizing of the gate length have caused the gate oxide to become so thin that current begins to leak across the gate even when there is no applied voltage. Therefore further improvement without minimizing the gate length is strongly required. Carrier mobility improvement has been seen as one of the best alternative for faster devices at lower power levels [5]. Strained silicon technology can offer significant performance enhancement to MOSFET devices [6] by increasing carrier mobility without having to make the devices become smaller [7], [8]. By stressing or straining, the silicon lattice lets electrons flow with less resistance. This will increase the drive current and make the transistor switch faster thus contributing to a higher clock frequency in integrated circuits (IC) with gate length downsizing to 60nm [9]. Another significant improvement in electrical performance for both n and p-channel device of strained Si with 25% Ge composition is demonstrated in [10]. In this paper we will study the performance enhancement by strained silicon as compared to conventional PMOS comprehensively with the help of Silvaco TCAD process and device simulation tools. With the Tox of 16nm and 35% of Ge concentration, the VT for the strained Si and conventional PMOS is -0.5067V and - 0.9290V respectively. The drain induced barrier lowering (DIBL) for the SSPMOS is 0.3034V and the conventional PMOS is 0.4747V, which shows a better performance for strained silicon as compared to conventional PMOS. Consequently, the output characteristics were also obtained for SSPMos that showed an improvement of Drain current compared with conventional PMOS. II. DEVICE STRUCTURE AND PROCESS Both strained silicon PMOS with an added SiGe layer and normal conventional PMOS device without SiGe layers process simulation were carried out using ATHENA, Figure 1 shows the structure of both devices. The simulation process to create the strain silicon PMOS is similar to the conventional PMOS fabrication process. The fabrication of SSPMOS device starts by creating a silicon substrate with phosphorus doping of 2 x 1018 cm-3 and then a silicon layer with the thickness of 0.018ptm is deposited on the silicon 0-7803-9731-2/06/$20.00 ©2006 IEEE 924 Authorized licensed use limited to: UNIVERSITY TEKNOLOGI MALAYSIA. Downloaded on January 5, 2009 at 23:57 from IEEE Xplore. Restrictions apply.