44 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 1, FEBRUARY 2003 Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays Arifur Rahman, Member, IEEE, Shamik Das, Member, IEEE, Anantha P. Chandrakasan, Member, IEEE, and Rafael Reif, Fellow, IEEE Abstract—In this paper, analytical models for predicting inter- connect requirements in field-programmable gate arrays (FPGAs) are presented, and opportunities for three-dimensional (3-D) im- plementation of FPGAs are examined. The analytical models for two-dimensional FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with more than 20K four-input look-up tables, the reduction in channel width, interconnect delay and power dissipation can be over 50% by 3-D implementation. Index Terms—Field-programmable gate arrays (FPGA), Rent’s rule, three-dimensional (3-D) integrated circuit (IC), wire-length. I. INTRODUCTION T HERE are several options for implementing a digital in- tegrated circuit in silicon. In one end of the spectrum, one can use full-custom designs that require time-intensive de- sign, verification, and optimization to achieve maximal perfor- mance. On the other end of the spectrum, field-programmable gate array (FPGA)-based design can be used. In FPGA-based implementation, a design is mapped onto an array of reconfig- urable logic blocks that are interconnected by programmable in- terconnections [1], [2]. The fine-grain architecture in FPGAs is suitable for bit- and byte-level computation [1]. They can also be used as flexible logic resources for encryption, error cor- rections, address generations, etc. Although FPGA-based im- plementation requires fewer design iterations and has the ad- vantage of shorter time-to-market, the system performance and logic density in FPGA-based implementation is not as high as full-custom designs due to the area and performance overhead of programmable logic and interconnect. In some recent studies, it has been found that in SRAM-based FPGAs, 40%–80% of overall design delay and 90% of chip area are attributed to programmable interconnects [1], [3]. It has also been found that in SRAM-based FPGAs, as much as 80% of total power dissipation is associated with programmable inter- connects and clock networks [4]. Considering the area, delay, Manuscript received July 31, 2001; revised April 1, 2002. This work was supported by the MARCO Focused Research Center on Interconnects, under the Massachusetts Institute of Technology, by subcontract from the Georgia In- stitute of Technology. A. Rahman is with Polytechnic University, Brooklyn, NY 11201 USA. S. Das, A. Chandrakasan, and R. Reif are with Microsystems Technology Laboratories, Michigan Institute of Technology, Cambridge, MA 02139-4307 USA. Digital Object Identifier 10.1109/TVLSI.2003.810003 Fig. 1. Cross section of a 3-D IC based on low-temperature wafer bonding. and power dissipation overhead, the programmable interconnect is a key design element in FPGAs. It is desirable to incorporate innovative mapping and routing architectures that would result in higher logic density and lower interconnect delay. Currently, in the FPGA industry there is a growing interest to combine both application specific integrated circuit (ASIC) and FPGA func- tionalities on the same chip to form filed programmable system chips (FPSCs) that offer the benefits of both ASICs and FPGAs [5], [6]. However, the gate count on the ASIC portion and the number of programmable logic blocks on the FPGA side are often not sufficient for many applications. Recently, there have been renewed interests in three-dimen- sional (3-D) ICs to reduce interconnect delay and increase logic and memory density for future VLSI applications [7]–[13]. Three-dimensional ICs can be formed by monolithic vertical integration of multiple strata using wafer bonding, selective epitaxial growth, or recrystallization [9]–[13], where a stratum consists of a device layer and several interconnect levels. Cross section of a 3-D IC based on wafer bonding is shown in Fig. 1. In this particular technology, the interconnections between strata are formed by high aspect ratio vias etched through the thinned Si layer [9], [13]. In other 3-D IC technologies, based on epitaxial growth or recrystallization, conventional back end of the line (BEOL) processing can be used to form inter-stratum interconnects. By 3-D integration, significant reduction in wire-length and wiring-limited chip area can be achieved [8], [14]. Considering the overhead on delay and chip area due to the programmable interconnects, FPGA is an ideal candidate that can benefit significantly by 3-D integration. In this paper, opportunities for 3-D implementation of FPGAs are explored based on system-level modeling and analysis. Analytical models for predicting channel width in SRAM-based 2-D FPGAs are 1063-8210/03$17.00 © 2003 IEEE