Journal of Circuits, Systems, and Computers Vol. 16, No. 4 (2007) 577–588 c  World Scientific Publishing Company THEORETICAL AND EXPERIMENTAL EVALUATION OF THE PHASE NOISE BEHAVIOR OF A DUAL-LOOP FREQUENCY SYNTHESIZER FOR 5-GHz WLANs FOTIS PLESSAS * , SOFIA VATTI and GRIGORIOS KALIVAS Department of Electrical and Computer Engineering, University of Patras, Rion 26500, Greece * plessas@ee.upatras.gr Revised 8 May 2007 This paper presents the analysis and experimental evaluation of a modified dual-loop phase-locked loop synthesizer, using the phase noise transfer functions resulting from the linear model of the synthesizer. The different arrangement in the high-frequency loop, in contrast to previous reported series-connected dual-loop topologies, offers various advantages, such as improved phase noise, finer resolution, and lower spurious levels. Discrete elements are used to implement a prototype system for testing. This adds to the flexibility of the design and allows for experimental optimization of the loop trade-offs. The synthesizer generates signals in the 4850 MHz to 5050 MHz range with a 10 MHz resolution and can match the specifications for wireless LANs operating at 5 GHz. The design resulted in a prototype with very good characteristics suitable for future integration. Keywords : Phase-locked loop; frequency synthesizer; dual-loop architecture; wireless receiver; phase noise. 1. Introduction Due to the demands for modern WLAN technology in recent years, there is increas- ing need for systems operating at high radio frequencies in the range of 5 GHz. A critical subsystem for these applications is the frequency synthesizer which must exhibit low phase noise over a wide bandwidth, fast settling time and low spur level. The demand for wide bandwidth and low phase noise leads us to give increased attention to the system design. In this work, we reconsider dual-loop designs and put them in the context of broadband design at the 5GHz range. We propose a modified architecture, which through analysis and measurements proved to exhibit superior phase noise performance compared to other reported architectures. To demonstrate the validity of our approach the synthesizer is implemented using dis- crete components. Measurements give comparable results to theory and show that the proposed modified dual-loop architecture can lead to superior performance. 577