Superlattices and Microstructures 142 (2020) 106522 Available online 20 April 2020 0749-6036/© 2020 Elsevier Ltd. All rights reserved. GaAs 0.5 Sb 0.5 / In 0.53 Ga 0.47 As heterojunction dopingless charge plasma-based tunnel FET for analog/digital performance improvement Amit Bhattacharyya a , Manash Chanda b , Debashis De c, * a Department of Electronics and Communication Engineering, Haldia Institute of Technology, Haldia, 721657, India b Department of Electronics and Communication Engineering, Meghnad Saha Institute of Technology, Kolkata, 700150, India c Department of Computer Science and Engineering, Maulana Abul Kalam Azad University of Technology, Kolkata, 700064, India A R T I C L E INFO Keywords: Ambipolar Charge plasma Hetero-gate- dielectric Interface trap charges (ITCs) Linearity Analog/RF fgure Of merits (FoMs) ABSTRACT A dual side doping-less (DL) GaAs 0.5 Sb 0⋅5 /In 0.53 Ga 0.47 As heterojunction tunnel FET (DDL-HTFET) confguration together with hetero-gate-dielectric material (HfO 2 /SiO 2 ) has been proposed in this article. Hence, N þ -pocket with varying electron concentration has been implemented by changing the length of source-side channel (L SC ) beneath the gate. The impact of interface trap charges (ITCs) on the execution of the proposed device has been examined by initiating dual (donor and acceptor) sort of confned charges near the semiconductor/insulator intersection. An assessment has been carried out among proposed HTFET and Si-based devices having similar dimensions with respect to dc, analog/RF, and linearity distortion factors thoroughly in existence of ITCs. ATLAS simulations illustrate that the proposed DDL-HTFET is more protected in terms of per- formance deviation than its Si-based contenders with various ITCs existing at semiconductor/ insulator intersection. Hence, DDL-HTFET model can be a promising candidate for the low-power RF applications and can offer improved linearity and less distortion. 1. Introduction With latest development in the area of MOS technology, device dimensions are miniaturized to nanometer range [1]. Greater sub threshold swing (SS) (nearly higher than 60 mV/decade at room temperature) and high leakage current [2,3] have been reported as serious concerns for scaled devices. TFET has gained signifcant attention by surmounting these limitations. Owing to BTBT mecha- nisms for conduction purpose, TFET comprises less SS and reduced OFF-state current (I OFF ) but lower I ON and inferior ambipolar nature [4,5]. Plethora of TFET structures has been reported in literature to overcome the limitations. Mainly, the work function engineering [6–8], band-gap engineering [6,9], gate dielectric engineering [9,10], Core-shell architecture [11,12] and electrostatically doped (ED) gate underlap structure [13] are the most signifcant ones. Recently, the doping-less (DL) architecture has drawn enormous interest. Depending on the DL perception [12,14,15], P þ type (N þ type) source (drain) sections in a TFET can be implemented by the metal having suitable work function connecting with the semiconductor. In addition, DL-TFET suppresses the diffculties of RDF [16] and provides protection against sensitivity to parameter deviation [17]. Although, Si-based DL-TFET reveals a low I ON due to huge elec- tronic tunneling mass for silicon as well as poor lateral-electric feld inside the tunneling zone, identical concerning to traditional * Corresponding author. E-mail addresses: amit_elec06@yahoo.com (A. Bhattacharyya), manash.bst@gmail.com (M. Chanda), dr.debashis.de@gmail.com (D. De). Contents lists available at ScienceDirect Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices https://doi.org/10.1016/j.spmi.2020.106522 Received 18 January 2020; Received in revised form 22 March 2020; Accepted 11 April 2020