1551-3203 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TII.2019.2953071, IEEE Transactions on Industrial Informatics Abstract—Multilevel inverters (MLIs) have been extensively employed to improve the power quality of the photovoltaic (PV) systems. However, the need for large number of components, higher standing voltage, and high harmonic content in the output of a conventional MLI greatly affects the system efficiency. Asymmetrical MLIs have been therefore developed as a suitable alternative to address these issues. Current study aims at developing such a hybrid asymmetrical structure suitable for PV application that has a high level per component ratio and minimum standing voltage. The proposed MLI is assembled using a reduced switch H-bridge based (RSHB) MLI structure with n asymmetrical repeating units and different level doubling circuit (LDC) combinations. The two dc sources used in the repeating units are in the ratio of 1:n voltage ratio and using n such units, the proposed MLI structures, i.e., PS1 and PS2 can synthesize 4n+5 and 4n+7 levels, respectively at the output instead of 2n+3 levels with only RSHB MLI. Comparative analysis reveals that both PS1 & PS2 have fewer switches, low standing voltage, less power loss, and lower cost. A 3.9 kW standalone solar PV system is considered for performance evaluation of the PS1 structure applying both the selective harmonic elimination (SHE) and carrier-based pulse width modulation (PWM) control schemes. In light of this, dc-link voltage balancing and self-voltage balancing mechanism of the LDC are warranted. Extensive simulation of the proposed MLI is performed in MATLAB/Simulink platform under a change in modulation index, sudden load change, frequency change, and step change in solar insolation. Furthermore, theoretical and simulation findings are validated experimentally by performing similar tests on a prototype of the proposed seventeen-level MLI. Index Terms—Level doubling circuit (LDC), level per component ratio (LCR), multilevel inverter (MLI), photovoltaic (PV) system, pulse width modulation, standing voltage, switching loss I. INTRODUCTION ULTILEVEL inverters (MLIs) have been evolved as an emerging power electronics converter in recent years. MLIs can produce high-quality output with lower switching frequency operation, thereby reducing the voltage stress, harmonic in the output, electromagnetic interference, switching loss, etc., compared to conventional two-level inverters in the process of electrical energy conversion [1], [2]. Due to their competency in solving the above issues, research focus has attracted MLI for numerous applications such as electric drives, electric vehicles, railways, aircraft, and renewable energy systems [2]–[5]. By the proper arrangement of dc-link, semiconductor switches, diodes, and capacitors, MLI produces a staircase output. MLIs are broadly classified into three categories, such as single dc-source flying capacitor MLI (FC MLI), single dc-source diode clamped MLI (DC MLI), multiple dc-sources cascaded H-bridge MLI (CHB MLI) [6]–[9]. The CHB MLI offers many advantages in the context of voltage balancing, design complexity, size, and cost [5], [10]. Due to this reason, CHB topology is mostly considered by the researchers for advancement and also suitable for a range of low voltage (230 V) to a higher voltage (>10 kV) level application [11]. Reduction in number of semiconductor switches in MLI is the key concern among researchers. In this aspect, several MLI topologies have been developed in the recent past that addresses the aforementioned issues. In [12]–[14], an attempt has been made to reduce the number of device counts. These topologies require almost half the number of switches as required by a conventional CHB MLI. However, more voltage stress on the switches restricts their operation in high voltage applications. Meanwhile, few optimized MLI structures developed in [15], [16] requires less switch count to synthesize multiple levels at the output. Unlike the CHB MLI, these topologies can inherently generate negative levels. It is important to note that voltage stress is a major parameter that has to be taken care of while scheming the MLI for certain applications. Considering the above concern, the authors in [17], [18] have presented new MLI topologies with an approach to lessen the voltage stress as well as to reduce the device count. Utilization of dc sources with suitable magnitude is a well- known approach to generate multiple levels at the output. The topologies in [19], [20] are the examples that employ this approach. The authors have developed several algorithms for the determination of dc source magnitude to synthesize all the desired output voltage levels. The selection of suitable algorithms is a key factor that will result in generation of maximum possible levels with low voltage stress on the switches. Apart from the popularity and vast application of H- bridge based MLIs, the design of different hybrid MLI structures is also one of the current research themes. For instance, a compact module type MLI in [21], MLI in [15], [22], packed U cell MLI in [23], [24] produces multilevel output without the requirement of an H-bridge. In such a case to increase the number of levels, these modules/basic units can be cascaded. On the other hand, the invention of level doubling circuit (LDC) is a major contribution towards the advancement of MLI technology [25]. In order to double the number of levels with the same active switch count, LDCs in integration with MLI with different voltage magnitudes can be used [5], [26]. Different pulse width modulation (PWM) schemes are developed in recent years as a key concern for controlling the voltage and current quality by generating the appropriate Power Quality Performance Evaluation of Multilevel Inverter with Reduced Switching Devices and Minimum Standing Voltage Prabhat Ranjan Bana, Student Member, IEEE, Kaibalya Prasad Panda, Student Member, IEEE, and Gayadhar Panda, Senior Member, IEEE M