Performance optimisation of junctionless FET in nano regime using segmented channel - A 3D numerical simulation study S. Priscilla Scarlet a, * , B. Prasannanjaneyulu b , R. Srinivasan a a Department of IT, SSN College of Engineering, Kalavakkam, Tamilnadu, India b Department of EE, IIT Madras, Tamilnadu, India article info Article history: Received 16 May 2017 Received in revised form 10 August 2017 Accepted 11 August 2017 Available online xxx Keywords: VSTI BPJL SegFET SOIJL SegFET TCAD and f T abstract The performance of the planar junctionless devices is improved using corrugated substrate also known as SegFET device. Bulk and SOI based planar junctionless devices are inves- tigated for their performance enhancement using 3D numerical simulations. Four devices, (i) BPJLT - junctionless device on bulk planar substrate (ii) BPJL SegFET - junctionless device on bulk corrugated substrate (iii) SOIJLT - junctionless device on SOI planar substrate (iv) SOIJL SegFET - junctionless device on SOI corrugated substrate, are taken for study. BPJL SegFET and SOIJL SegFET devices are compared against BPJLT and SOIJLT devices to find out the benefit of the corrugated substrate in junctionless devices. The parameters I ON ,I OFF , I ON /I OFF ratio and unity gain frequency (f T ) are used for comparison. Replacing the planar substrate with corrugated substrate improves the I ON /I OFF ratio but degrades f T . The impact of corrugated substrate on bulk device is more compared to SOI device. The impact of VSTI region (W VSTI ) and stripe region widths (W SPACE ), and permittivity of VSTI region (K VSTI ) are also analyzed. While better I ON /I OFF performance can be achieved by using higher permittivity in VSTI region and by increasing the VSTI width, higher f T is obtained by using higher stripe width. A full factorial DOE simulation has also been performed in order to rank the above three parameters with respect to I ON ,I OFF and I ON /I OFF at the end. An overall ranking has also been provided which predicts W VSTI to be the most sensitive parameter irrespective of I ON ,I OFF or I ON /I OFF . © 2017 Elsevier Ltd. All rights reserved. 1. Introduction Many solutions have been proposed to mitigate the short channel effects (SCE) faced by the CMOS devices. Multigate devices, and junctionless devices are the two important solutions to reduce the SCE. Even though the multi-gate structures are potential alternatives for the CMOS devices [1,2] since the process steps are incompatible with the existing CMOS technology other planar solutions are sought. Junctionless tri-gate device concept was introduced in 2010 [3], and it offers better SCE performance [4,5] and simple processing steps. Since its introduction, junctionless operation has been investigated on many different structures, including planar junctionless devices [6], junctionless operation on a square shaped tube with gate inside [7], and junctionless Silicon nanotubes [8,9]. Segmented-channel bulk MOSFET (SegFET) structure discussed in Refs. [10e12] gives good control over the SCE in nano scale range. The channel region of the SegFET device consists of one or * Corresponding author. E-mail address: lillypushpam5@gmail.com (S.P. Scarlet). Contents lists available at ScienceDirect Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices http://dx.doi.org/10.1016/j.spmi.2017.08.031 0749-6036/© 2017 Elsevier Ltd. All rights reserved. Superlattices and Microstructures xxx (2017) 1e11 Please cite this article in press as: S.P. Scarlet et al., Performance optimisation of junctionless FET in nano regime using segmented channel - A 3D numerical simulation study, Superlattices and Microstructures (2017), http://dx.doi.org/10.1016/ j.spmi.2017.08.031