IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 7, NO. 3, SEPTEMBER 1999 321 The Design of a SRAM-Based Field-Programmable Gate Array—Part II: Circuit Design and Layout Paul Chow, Member, IEEE, Soon Ong Seo, Jonathan Rose, Member, IEEE, Kevin Chung, Gerard P´ aez-Monz´ on, and Immanuel Rahardja Abstract—Field-programmable gate arrays (FPGA’s) are now widely used for the implementation of digital systems, and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these archi- tectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. In Part I of this paper, we described the high-level architectural design of a static random- access memory programmable FPGA. This paper will address the circuit-design issues through to the physical layout. We address area-speed tradeoffs in the design of the logic block circuits and in the connections between the logic and the routing structure. All commercial FPGA designs are done using full-custom hand layout to obtain absolute minimum die sizes. This is both labor and time intensive. We propose a design style with a minitile that contains a portion of all the components in the logic tile, resulting in less full-custom effort. The minitile is replicated in a 4 4 array to create a macro tile. The minitile is optimized for layout density and speed, and is customized in the array by adding appropriate vias. This technique also permits easy changing of the hard-wired connections in the logic block architecture and the segmentation length distribution in the routing architecture. Index Terms—FPGA, FPGA architecture, FPGA circuit design, field-programmable gate arrays, SRAM programmable. I. INTRODUCTION T HE design and implementation of field-programmable gate array (FPGA) technology is rarely described in the literature because much of the information is proprietary. In [1], we describe some of the prior work and show the high- level architectural decisions used to select the logic block and routing architecture for the design of a high-performance FPGA. A symmetric array of hard-wired four-input logic blocks with a segmented routing architecture was selected. Fig. 1 illustrates such an array. Manuscript received May 31, 1996; revised December 8, 1998. This work was supported under a MICRONET Network of Excellence Grant. P. Chow and J. Rose are with the Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ont., Canada M5S 3G4 (e-mail: pc@eecg.toronto.edu). S. O. Seo is with ATI Technologies, Thornhill, Ont., Canada L3T 7N6. K. Chung is with Xilinx Toronto Development Centre, Toronto, Ont., Canada M5S 2T9. G. P´ aez-Monz´ on is with National Semiconductor Corporation/Cyrix-West, Santa Clara, CA 95052-8090 USA, on leave from CEMISID, Universidad de Los Andes–Venezuela, M´ erida-M´ erida 5101, Venezuela. I. Rahardja is with Aristo Technology Inc., Cupertino, CA 95104. Publisher Item Identifier S 1063-8210(99)04561-8. Fig. 1. Architectural definitions. This paper reports on the circuit design and layout con- siderations that were made during the implementation of our prototype chip. In Section II, we discuss the various circuit- design issues that must be considered. A novel layout style for FPGA’s is presented in Section III. The area, speed, and performance of the chip are given in Section IV. Finally, Section V provides some conclusions. II. CIRCUIT DESIGN In this section, we discuss the circuit-level design of the FPGA architecture described in [1]. The technology used in this design is a 1.2- m two-level metal n-well complimentary metal–oxide–semiconductor (CMOS) process. Fig. 2 illustrates the signal path starting at the input of an L3-4.2 lookup table (LUT), which was selected in Section II of [1]. Following the LUT is an output stage that contains a multiplexer to select the latched or unlatched version of the output before the signal is driven through a connection block (C block) onto the routing tracks. The signal then goes through one switch block (S block), or a number of S blocks, before it enters another C block where it will reach the input of the next logic block. In the following sections, we discuss issues that arose in the design of this path. Simulation with HSPICE 1 was used to evaluate different circuit options. 1 HSPICE User’s Manual, Meta-Software Inc., Campbell, CA 95008 USA. 1063–8210/99$10.00  1999 IEEE