COMMUNICATION 1808265 (1 of 9) © 2019 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim www.advmat.de Negative Transconductance Heterojunction Organic Transistors and their Application to Full-Swing Ternary Circuits Hocheon Yoo, Sungmin On, Seon Baek Lee, Kilwon Cho, and Jae-Joon Kim* Dr. H. Yoo, S. On, Prof. J.-J. Kim Department of Creative IT Engineering Pohang University of Science and Technology Pohang 790-784, Republic of Korea E-mail: jaejoon@postech.ac.kr S. B. Lee, Prof. K. Cho Department of Chemical Engineering Pohang University of Science and Technology Pohang 790-784, Republic of Korea The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/adma.201808265. DOI: 10.1002/adma.201808265 H-TRs typically have an asymmetric device architecture in which one electrode makes contact with an n-type semicon- ductor and the other electrode makes contact with a p-type semiconductor, creating a p–n junction at the middle of the channel. In H-TRs, the drain current (I D ) does not monotonically increase with the increased gate voltage bias (|V G |), as in a conventional transistor. The I D curve of an H-TR has a peak value in the mid-range of V G . As a result, negative transconduct- ance (NTC) can be observed in the region where I D decreases with increasing |V G |. By simply replacing one transistor with a H-TR in a conventional inverter circuit, ternary inverter circuits (i.e., three-valued logic) can be implemented. [12,15,17] Over the gate voltage range in which NTC occurs in H-TRs, both types of transistors (i.e., H-TR and conventional unipolar transistors) show comparable I D , providing similar pull-up and pull-down resistance. Hence, the V OUT of a ternary inverter becomes ≈V DD /2, and consequently, three distinct logic states (G ND , V DD /2, V DD ) can be obtained. However, challenges still exist. First, the ternary inverters using H-TRs tend to show incomplete circuit operation in which the output voltage (V OUT ) does not fully swing between V DD and G ND (Figure S1, Supporting Information). [15,17] Because H-TRs exhibit anti-ambipolar characteristics (i.e., an inverted ambi- polar transfer characteristic) [11,22,23] such that either the p- or n-type semiconductor is completely depleted as V G approaches V D (i.e., V G ≈ V D ) due to a high energy barrier (Figure S2, Supporting Information), H-TRs have relatively lower on cur- rents (I ON ) than do typical n- or p-type transistors. Hence, the I ON /I OFF ratio of H-TRs is relatively low. V OUT cannot be fully pulled down (or pulled up) because the I ON of the H-TR is not sufficiently higher than the I OFF of the counterpart pull-up (or pull-down) transistor in the same inverter. Several studies have demonstrated a higher I ON /I OFF ratio in H-TRs by replacing one semiconductor (i.e., either p- or n-type semiconductor) with an ambipolar semiconductor layer that offers both hole and electron conduction. [4,6,8] However, the crucial issue that limits the performance of the ambipolar semiconductor-based circuit is the large contact resistance (R C ) at the interface between the ambipolar semiconductor and a metal electrode due to the Schottky barrier (SB). Ambipolar semiconductors must be able to inject both electrons and holes, and thus, a large SB-induced contact resistance tends to exist. [24–26] As a result, a full V OUT Multivalued logic (MVL) computing could provide bit density beyond that of Boolean logic. Unlike conventional transistors, heterojunction transistors (H-TRs) exhibit negative transconductance (NTC) regions. Using the NTC characteristics of H-TRs, ternary inverters have recently been demonstrated. However, they have shown incomplete inverter characteristics; the output voltage (V OUT ) does not fully swing from V DD to G ND . A new H-TR device structure that consists of a dinaphtho[2,3-b:2′,3′-f ]thieno[3,2-b]thiophene (DNTT) layer stacked on a PTCDI-C13 layer is presented. Due to the con- tinuous DNTT layer from source to drain, the proposed device exhibits novel switching behavior: p-type off/p-type subthreshold region /NTC/ p-type on. As a result, it has a very high on/off current ratio (≈10 5 ) and exhibits NTC behavior. It is also demonstrated that an array of 36 of these H-TRs have 100% yield, a uniform on/off current ratio, and uniform NTC characteristics. Furthermore, the proposed ternary inverter exhibits full V DD -to-G ND swing of V OUT with three distinct logic states. The proposed transistors and inverters exhibit hysteresis-free operation due to the use of a hydrophobic gate dielec- tric and encapsulating layers. Based on this, the transient operation of a ternary inverter circuit is demonstrated for the first time. Heterojunction Transistors Multivalued logic (MVL) has emerged as a promising alternative to conventional Boolean computing [1–3] because MVL potentially offers efficient digital computing by reducing chip area and thus power dissipation. Recently, heterojunction transistors (H-TRs) based on various semiconductor materials have been studied for MVL implementation utilizing their negative differential resistance or transconductance characteristics. The materials for H-TRs include transition metal dichalcogenides (TMDs), [4–13] organic semiconductors, [14–16] graphene, [17] and hybrid material combinations, including carbon nanotube (CNT)-molybdenum disulfide (MoS 2 ), [18] organic-MoS 2 , [19,20] and indium gallium zinc oxide (IGZO)-CNT. [21] Adv. Mater. 2019, 1808265