0733-8724 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JLT.2015.2503120, Journal of Lightwave Technology 1 Comprehensive Design Space Exploration of Silicon Photonic Interconnects Meisam Bahadori, Student Member, IEEE, S´ ebastien Rumley, Member, IEEE, Dessislava Nikolova, and Keren Bergman, Fellow, IEEE, OSA Abstract— The paper presents a comprehensive physical layer design and modeling platform for silicon photonic interconnects. The platform is based on explicit, closed-form expressions for optical power penalties, derived for both signal-dependent and signal-independent noise contexts. Our models agree well with reported experimental measurements. We show how the modeling approach is used for the design space exploration of silicon photonic links and can be leveraged to optimize the wavelength division multiplexed (WDM) capacity, evaluate the scalability, and study the sensitivity of the system to key device parameters. We apply the methodology to the design of microring-based silicon photonic links, including an evaluation of the impairments associated with cascaded ring modulators, as well as the spectral distortion and crosstalk effects of demultiplexer ring arrays for non-return-to-zero (NRZ) on-off keying (OOK) modulated WDM signals. We show that the total capacity of a chip-to- chip microring-based WDM silicon photonic link designed with recently reported interconnect device parameters, can approach 2 Tb/s realized with NRZ-OOK data modulation and 45 wave- lengths each modulated at 45 Gb/s. Index Terms— Optical interconnects, microring resonators, silicon photonics I. I NTRODUCTION W ITH THE vast rise in parallel multicore architectures, the scalability of computing performance is increas- ingly reliant on the availability of high-bandwidth, energy efficient data communications infrastructure. Silicon photonics has attracted considerable interest [1]–[3] as an emerging tech- nology that can offer close integration of CMOS electronics with optical devices [4], [5]. This technology has the potential for delivering ultra high bandwidth interconnect solutions that are at the same time energy efficient and available at low cost. Silicon photonics has been proposed for designing efficient networks-on-chip [6]–[10], for supporting global interconnects for datacenters [11], and high performance computing (HPC) systems [12], [13]. It has been also presented as an enabling technology for realizing Exascale computing systems (i.e. Supercomputers capable of realizing 10 18 operations per sec- ond) [14], [15]. The chip-scale integration of electronics and photonics may further alleviate the limitations of electronic chips in terms of I/O pin count [16], [17]. Although multiple experimental demonstrations of silicon photonic devices, sub-systems or systems [18]–[21] have been reported in the last decade, the technology is still young and only recently emerging for commercial systems adoption. Significant design space exploration is required to understand The authors are with the Department of Electrical Engineering, Columbia University, New York, NY 10027, USA. Email: {mb3875, sr3061, dnn2108, kb2028}@columbia.edu. the performance and impact of silicon photonics for comput- ing interconnects. The design methodology for implementing electro-optical interfaces at the transmitters and receivers must be developed. In particular, it is critical to understand how silicon photonic optical modulators, multiplexers, and demul- tiplexers can be combined to obtain optimized, thus efficient, WDM links. In this paper, we present a uniquely comprehensive mod- eling platform for efficiently exploring the design space of silicon photonic interconnects, from the physical layer to the link-level analysis. We concentrate our efforts on microring- resonator-based links, as they offer the highest bandwidth density and most energy efficient performance among current silicon photonic interconnect devices [22]–[24]. Microring resonators (MRR) can be designed to perform several inter- connect functions and represent the key building blocks of silicon photonic systems [25], [26]. MRRs can be used both as active modulators and switches, as well as wavelength- selective passive filters. When acting as modulators [27]–[33], they leverage plasma dispersion effects of silicon [34]–[36] which provides an efficient way of changing the effective refractive index of the ring by injecting or depleting charge carriers. Such modulation scheme has proven to be capable of delivering high-speed modulations, e.g. 10 Gb/s or higher with low energy consumption [22], [24], [37]–[41]. When used as demultiplexers, a ring operates as a passive drop filter whose resonance is tuned to a specific channel wavelength [23], [42], [43]. In this case, fine-tuning is carried out via integrated heaters that are implemented on top of the silicon microring [44], [45]. First order or higher order add-drop filters have been fabricated and demonstrated in recent years [46], [47]. MRRs are generally very sensitive to thermal fluctuations [48], [49], but several stabilization mechanisms (e.g. wavelength- locking schemes) have been proposed in recent years to redress this vulnerability [50]–[55]. MRRs can also switch multiple wavelengths from one waveguide to another and spatially route them to another path [56]–[60]. Due to their small size, many microrings can be cascaded on a single on-chip bus waveguide, facilitating the dense wavelength-division-multiplexing design and operation of the link [61]–[63]. However, WDM links may suffer from spectral degradation of channels and inter-channel crosstalk [64]–[72]. These impairments eventually put an upper limit on both the modulation speed of each channel and on the number of channels, thus placing an upper bound on the maximum aggregate rate of the link [73], [74]. In this paper, we present the design and modeling platform