IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998 1111 Design and Implementation of a 5 5 trits Multiplier in a Quasi-Adiabatic Ternary CMOS Logic Diego Mateo and Antonio Rubio Abstract— Adiabatic switching is a technique to design low- power digital IC’s. Fully adiabatic logics have expensive silicon area requirements. To solve this drawback, a quasi-adiabatic ternary logic is proposed. Its basis is presented, and to validate its performance, a 5 5 ternary digit multiplier is designed and implemented in a 0.7- m CMOS technology. Results show a satisfactory power saving with respect to conventional and other quasi-adiabatic binary multipliers, and a decrease of the area needed with respect to a fully adiabatic binary one. Index Terms— Adiabatic switching, low-power digital design, low-power multiplier, ternary CMOS logic. I. INTRODUCTION T HE design of digital very low-power integrated circuits has become a strategic topic of research [1]. Different techniques at the different levels of the design can be applied to achieve low consumption. One of these techniques is adiabatic switching [2]–[6], which is based on two basic principles: slowing down the transport of charge, and recovering the charge stored in the parasitic capacitors. The different adiabatic logics that have been developed until now can be classified as fully adiabatic logics [2], [3] and nonfully or quasi-adiabatic logics [4], [6]. The advantage of the first logics over the others is their smaller consumption, and the disadvantage is the increase of the silicon area required, due basically to the implementation of computational reversibility needed to obtain recovery of charge [2]. An alternative to this problem is presented in this paper: a quasi-adiabatic ternary (QAT) CMOS logic is proposed in order to obtain the ternary circuit benefits of reducing the area [7]. The consumption of the QAT logic is similar or smaller than the dissipation in other quasi-adiabatic logics. The basis of the logic is presented in Section II. In Section III, the implementation and measurement of a 5 5 trits (ternary digits) multiplier are shown, and in Section IV, its performances are compared with those from other multipliers. In Section V, the conclusions are summarized. II. QAT CMOS LOGIC In this section, the basis of the logic is presented: first, its basic cells; then, how to interconnect them to build a more Manuscript received October 30, 1997; revised November 24, 1997. This work was supported by the Spanish Research Commission (CICYT) under Project Contract TIC95-0469. The authors are with the Department of Electronic Engineering, Universitat Polit` ecnica de Catalunya, 08034 Barcelona, Spain. Publisher Item Identifier S 0018-9200(98)03106-0. Fig. 1. Structure, symbol, and clocks of the STI (simple ternary inverter). complex system; and finally, the existing compromise between noise margins and energy consumption. A. Basic Cells Adiabatic logics usually consider four basic phases in one computational cycle for each logic stage (see Fig. 1): 1) input validation; 2) output evaluation: power supplies (clocks) are activated by slow ramp signals, computing the input information; 3) hold: the value of the output is read by the next gate; 4) output recovery: the clocks are deactivated, returning the output to its previous value. In the QAT logic, the same four phases are used, but are adapted to the ternary valuation. The algebra used to implement the ternary valuation is the Yoeli–Rosenfeld algebra [8], which allows easily integrated CMOS implementations [9]. The three logic levels (“ 1,” “0,” “1”) are represented by the voltage levels , , and , respectively, with . Ternary gates presented here are based on the dynamic ternary gates shown in [9]. They are made from conventional binary CMOS structures with a maximum positive power supply voltage chosen in such a way that, when an intermediate voltage is applied to the input of the gate, both types of transistors and are off. This condition implies that (1) where , . Special nonconstant power supplies are used to give and recover the energy used to compute. They use slow ramp signals to achieve adiabatic transfer of charge. The simple ternary inverter (STI) is implemented from a conventional CMOS inverter by using the clock signals and as 0018-9200/98$10.00  1998 IEEE Authorized licensed use limited to: UNIVERSITAT POLITECNICA DE CATALUNYA. Downloaded on September 20,2022 at 10:47:20 UTC from IEEE Xplore. Restrictions apply.