A Digital CMOS DNA Chip Alexander Frey, Meinrad Schienle, Christian Paulus, Zou Jun, Franz Hofmann, Petra Schindler-Bauer, Birgit Holzapfl, Melanie Atzesberger, Gottfried Beer, Michaela Fritz, Thomas Haneder, Hans-Christian Hanke, and Roland Thewes Infineon Technologies AG Munich / Regensburg, Germany alexander.frey@infineon.com Abstract— A fully electronic medium density DNA micro array is presented using a CMOS process extended by gold electrodes. The chip provides 128 sensor sites, in-sensor site current-mode A/D conversion, peripheral circuitry including bandgap and current references, D/A-converters to provide electrode bias voltages, calibration circuitry, and a 6 pin interface for power supply and serial digital data transfer. I. INTRODUCTION DNA sensor arrays integrated on CMOS chips allow fully electronic readout of biological information. Compared to state-of-the-art optical methods they offer the advantage that expensive optical setups containing CCD cameras, lenses, etc. are not needed. Potential key improvements of fully electronic systems are more robust and easier operation. These features enable applications in new fields and markets like diagnosis in doctors’ offices, food control, etc. Recently, a number of achievements along the way to fully electronic DNA chips have been published: Bio- compatible interface- and transducer-materials were reliably integrated into a standard CMOS environment [1, 2]. Array- compatible high-precision analog pixel circuits suitable to process small current signals within a large dynamic range were presented in [1, 3, 4]. However, the CMOS DNA sensor arrays presented so far are designed to allow high flexibility proof of principle measurements in a laboratory environment. Therefore they have a chip architecture suitable for great testing flexibility. In this paper we present a digital CMOS DNA chip which combines the previous achievements within an electronic system which represents a cost optimized, robust and user friendly solution. The new chip system integration is described and the circuit blocks used are discussed. Experimental data of an electrical characterization of a calibration circuit and electrochemical measurements are reported. II. CHIP ARCHITECTURE A. Overview The sensor principle used is based on the electrochemical redox cycling technique and is briefly explained in Fig 1. A detailed discussion of the sensor principle is given in [5]. Fig 2. shows a schematic diagram of the chip architecture containing the most important circuit blocks of the chip. The core is a 128 sensor array with in-pixel analog-to-digital conversion [3]. Electrode bias voltages are generated by D/A converters. Each pixel circuit has a calibration input which can optionally be activated by an on-chip, high precision, calibration engine. Bias voltages and currents are derived from a bandgap circuit. In the periphery the potentiostat [4] is shown. The chip is powered with two pins. Four pins are used for serial data communication. Interface registers control the operation mode of the chip, address the pixel position decoder, store the values of the electrochemical bias voltages and control the calibration engine. For a more detailed description of the chip architecture the data path is schematically shown in Figure 3. The bandgap reference voltage together with a resistor is used to generate a bias current. This current is mirrored into two serially connected resistor strings. A tail resistor in that current path is used to adjust the midpoint voltage between the two resistor strings to roughly VDD/2. This voltage is used to bias the potentiostat and defines the analog ground of the system. With respect to this voltage the positive oxidation and negative reduction potentials are determined by the digital control signals Select_V Generator and Select_V Collector accordingly. The selected electrochemical bias voltages are buffered to drive the 128 pixel regulation loop operational amplifiers. Together with the potentiostat regulation loop, the working electrodes potentials are biased typically to ±200mV with respect to analog ground [4] to 2915 0-7803-8834-8/05/$20.00 ©2005 IEEE.