International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.3, June 2015 DOI : 10.5121/vlsic.2015.6306 59             Simi Zerine Sleeba and Mini M.G. Department of Electronics Engineering, Government Model Engineering College, Cochin University of Science and Technology Kochi, India ABSTRACT The scalability, modularity and massive parallelism exhibited by Network on chip(NoC) interconnects make them highly suitable for the inter core communication framework of multiprocessor system-on-chip (MPSoC) designs. Routers play the most vital role in transferring flits through the network, hence efficient microarchitecture and cost effective routing algorithms are highly essential for modern NoC routers. Elimination of buffers and deflection routing help to achieve energy and area efficiency of these routers. The advantages of bufferless and buffered designs can be combined by using a minimum number of side buffers to store a fraction of deflection flits in the router. In this paper, we propose a routing algorithm based on weighted deflection of flits for minimally buffered deflection routers. Evaluations on 4x4 and 8x8 mesh NoC using synthetic workloads as well as benchmark applications demonstrate that deflection rate and average network latency are significantly reduced in comparison with the state of the art NoC routers. Performance analysis of the newly proposed algorithm shows that the network saturation point improves by 26% compared to earlier designs in this domain. KEYWORDS Network on Chip, Deflection routing, Minimal buffering, Average Latency 1. INTRODUCTION As technology scaling reduces the feature size to nanolevels, a large number of intellectual property cores are being integrated on to a single chip[1]. Such chips can execute applications that demand extensive amounts of parallel processing. Hence there is an ever increasing demand for on chip interconnects capable of handling huge amount of data. Traditional bus based interconnects are no longer suitable for MPSoCs with hundreds and thousands of cores. NoCs emerge as a promising design choice for realising efficient on chip interconnections as they largely alleviate the limitations of bus based interconnects. Generally, MPSoCs employ a regular mesh topology as in Figure 1. Each Processing Element (PE) is connected to a local switching element called router(R) by means of a network interface. Each PE is either a processor core (with built-in L1 cache) or a slice of shared L2 cache. Requests