A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process–voltage–temperature variations C.B. Kushwah a , S.K. Vishvakarma a,n , D. Dwivedi b a Nanoscale Devices, VLSI Circuit & System Design Lab, Electrical Engineering, IIT, Indore, MP, India b System Technology Group, IBM, Bangalore, KA, India article info Article history: Received 6 May 2015 Received in revised form 3 January 2016 Accepted 28 February 2016 Keywords: Boost-less FinFET Process–voltage–temperature SRAM Sub-threshold Ultra-low power abstract A novel 20 nm FinFET based 7T SRAM cell is presented. Proposed 7T SRAM cell involves the breaking-up of feedback between the true storing nodes which enhances the write-ability of the cell at ultra-low voltage power supply without boosted supply and write assist. The read decoupling and feedback cutting makes proposed 7T SRAM cell more robust to process variations in sub-threshold regime. For proposed 7T SRAM cell, the mean and standard-deviation (μ/σ) ratio of hold static noise margin is 31.5% higher than that of conventional iso-area 5T SRAM cell at 0.5 V VDD. The 7T SRAM cell has 66.4% higher μ/σ of read margin as that of 5T SRAM cell at 0.25 V VDD. The write static noise margin of 7T SRAM cell is 50% of VDD for all VDD values whereas 5T SRAM cell fails to write. During write ‘0’, the proposed cell con- sumes only 0.11  power as that of 5T SRAM cell at 0.8 V VDD. The read operation of 7T SRAM cell consumes 0.34  lesser power than 5T SRAM cell read operation for all values of bit-line capacitances at 0.2 V VDD. At 0.2 V VDD, the 7T SRAM cell has 0.46  lower write ‘0’ delay as that of 5T SRAM cell. The write delay of 7T SRAM cell is 0.32  lower as that of 5T SRAM cell at 0.8 V VDD. The techniques used by the proposed 7T SRAM cell allow it to operate at ultra-low voltage supply without any write assist in 20 nm FinFET technology node. & 2016 Elsevier Ltd. All rights reserved. 1. Introduction To achieve higher reliability and longer battery life for implanted medical instruments, wireless body sensing networks and portable IoT devices, ultra-low power on-chip memory can be viable solu- tion. Operating a SRAM in the sub-threshold region can reduce the power consumption to minimum possible range. In sub-threshold regime, the data stability of SRAM cell is a severe problem and worsens with the scaling of MOSFET in sub-nanometer technology. Moreover, the intra and inter-die variations reduces the yield of SRAMs which are more susceptible to failure in sub-nanometer regime [1–3]. Therefore, the use of multi-gate solid-state device like FinFET gives better channel control and enables SRAM scaling at the traditional rate. This would result in smaller die sizes [4–7] as compared to that obtained using conventional MOSFETs. In addi- tion, the thin body of a multi-gate device is typically un-doped or lightly doped. Thus, the random dopant fluctuation is significantly decreased, which results in the reduction of threshold voltage (V TH ) variation [8]. On the other hand, some popular assist techniques are used to maintain both desired write-ability and read stability of SRAM arrays. These techniques include lower column supply voltages during write, bit-line (BL) and word-line (WL) bias, pulsed bit- lines, read and write assist column circuitry. These techniques aim to increase the array robustness with smaller cells, but necessarily lower array efficiency, resulting in larger area [9]. Different topologies (7T, 8T and 9T) and techniques (feedback cutting and read decoupling) have also been proposed to address the above issues to an extent [10–14]. To reduce area and power the single bit-line SRAM cell was used. The single bit-line cell provides higher density and consumes lesser power than using a bit-line pair. The single-ended 5T SRAM cell as shown in Fig. 1(a) is attractive due to its reduced area with considerable active and standby power saving as compared to conventional 6T SRAM cell. However, writing a ‘1’ through an NMOS pass transistor in 5T SRAM cell is a design challenge. This was achieved by applying boosted supply (a voltage greater than cell's power supply) at gate terminal of access transistor M5. This boosted supply was generated from an additional circuitry which increases area overhead. Another severe problem of 5T SRAM cell is severely degraded read stability as compared to conventional 6T SRAM cell [15]. Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/mejo Microelectronics Journal http://dx.doi.org/10.1016/j.mejo.2016.02.010 0026-2692/& 2016 Elsevier Ltd. All rights reserved. n Corresponding author. Tel.: þ91 732 4240719; fax: þ91 731 2361482. E-mail address: skvishvakarma@iiti.ac.in (S.K. Vishvakarma). Microelectronics Journal 51 (2016) 75–88