International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-8 Issue-11, September 2019 1645 Published By: Blue Eyes Intelligence Engineering & Sciences Publication Retrieval Number K18920981119/2019©BEIESP DOI: 10.35940/ijitee.K1892.0981119 Efficient Kernel Template AES Algorithm to Minimize Power Consumption and Maximize Security in Low Power Application Abstract— Cryptography involved in offering of secure data by generation of secret key through encryption process. At present, almost every applications require security scheme due to increased threats. Low power applications are limited to power sources where incorporation of attacks leads to certain challenges in terms of reduced throughput, data loss and increased power consumption hence it is necessary to adopt effective security scheme for low power application. Generally, in power circuits advanced encryption standard (AES) is incorporated which is defined as S-box. This substitution box is designed by 2 transformations (i.e) inversing the multiplication part in Galois field directed with modified affine transformation. The limitation of S-Box is more time and power consumption. In this paper, proposed a kernel based AES scheme for improving the performance of low power application. The proposed Kernal approach uses logic gate design with cipher text operation. The Kernel -AES technique is implemented in CMOS devices with 45nm standard cell technology. Results obtained for proposed Kernel-AES approach provides reduced power consumption rate of 28.5A which is comparatively less than conventional AES technique. Keywords—Cryptography, XOR, Kernel, AES, Cipher text I. INTRODUCTION At present cryptography is considered as major concern for every technological aspects. In cryptographic devices physical properties involved in extraction of secret information. For effective prevention of low power application from several attacks cryptographic technique need to be implemented. The implementation of attack in the circuit leads to leakage of information and leakage of information. Information leakage in circuit increases utilization of heat, timing, power and electromagnetic field. Attacker able regain information through the processed devices in form of ciphertext and plaintext while attackers focused on cryptographic key. Cryptography technique involved in provision of secure and protection for plaintext by means of secret key. This secret key has been generated in the encryption process also known as cipher texting. Cryptography has been widely adopted in vast fields such as mobile handsets, military, banking and smart cells [1]. The major of the application uses Advanced Encryption Standard (AES) for cyber security for improving adaptability. Even though AES subjected to side-channel attack due to inbuilt substitution box [2, 3]. Revised Manuscript Received on September 2, 2019. V.Nandan, Research Scholar, Department of Elect & Comm Engineering, Department of Elect & Comm Engineering,Veltech Rangarajan Dr.Sagunthala R& D, Inst. of science & Technology, Tamilnadu, India. Email: vnandanece@gmail.com R. Gowri Shankar Rao, Professor, Department of Physics,Veltech Rangarajan Dr.Sagunthala R& D, Inst. of science & Technology, Tamilnadu, India.Email: gsrvtu@gmail.com For Galois field (2m) involves process of substitution permutation network and fiestel architecture with arithmetic function also known as substitution function. In cipher application inverse process has been considered as modern application. Few standard AES cipher operation adopted inversion of GF(2) 8 and the affine transform GF(2) 8 . Due to light weight process AES algorithm has been adopted in several cryptography application process [4]. In other hand, circuit design involved in construction of functions of heuristic approach. Those approaches are minimal complex with exponential characteristics with calculation of time and inbuilt components. This methods are involved in construction of minimal budget components. Heuristic method involves several operation such as matrix, arithmetic and complex function. In low power application it is necessary to minimize power utilization level but those are in IP construction level. In this IP based construction power levels are build at transistor level. Through analysis of power levels in low power application now researchers focused towards gate level power optimization techniques [5]. In this scenario adoption of AES algorithm is complex for achieving desirable throughput, clock speed and assists in library due to arrangement complexity, scheduling and dynamic nature. Another challenge associated with AES circuit is calculation of power utilization hence in existing researches it is suggested that segments of sub-bytes which is S-box provides complete power utilization of low power applications. The S-box uses clock those are smaller in nature since it is constructed through folding circuit several times. The folding of circuit causes minimal impact over minimal energy utilization. In existing reduction of power is still challenging hence few researchers focused on development of block ciphers for prevent attack and reduce energy consumption rate [6, 7]. In this paper, kernel based AES cryptography technique modeling is implemented for efficient performance of low power applications. The proposed technique is implemented in CMOS devices with 45nm standard cell technology. In first step, designed as simple logic gates for CMOS technology. In next step, Kernel based technique is implemented integrated with AES approach for improving security in low power application specifically for smart cards, RFID tags and microcontroller. V.Nandan, R. Gowri Shankar Rao