A 1.7-mW Dual-Band CMOS Frequency Synthesizer for Low Data-Rate sub-GHz Applications Calogero Marco Ippolito, Alessandro Italia, and Giuseppe Palmisano Università di Catania, Facoltà di Ingegneria, DIEES V.le A. Doria 6, 95125 Catania, Italy Email: {cippolito, aitalia, gpalmisano}@diees.unict.it Abstract—In this paper, an ultra low-power wideband frequency synthesizer is demonstrated in a 90-nm CMOS technology. The circuit is intended for low data-rate sub-GHz transceivers and is based on a programmable integer-N phase-locked loop. The frequency synthesizer in cooperation with divide-by-two frequency dividers is able to provide quadrature LO signals in the 300-470 MHz and 750-950 MHz RF bands with a 150-kHz frequency step. It provides a phase noise better than -91 dBc/Hz at 150-kHz offset frequency for all the supported channels. The measured settling time is around 350 µS and the reference spurs are lower than -48 dBc. The power consumption of the frequency synthesizer is only 1.7 mW from a 1.2-V supply. I. INTRODUCTION Ultra low-power devices for low data-rate communication systems are the key components to enable advanced healthcare treatments [1]-[3], innovative home and automotive applications, and densely distributed sensor networks [4]-[5]. These applications have common requirements, such as high nodes autonomy (10 years) and small physical size. The operating frequency bands are lower than 1-GHz and the data rate does not exceed some hundreds kbit/s. The frequency synthesizer is one of the most critical building blocks of the RF front-end for such low data-rate networks. Indeed, the constraint of a very low power consumption imposes severe limits to the VCO phase noise and tuning range performance [6]-[9]. Moreover, the programmable divider must be carefully designed to support different frequency bands while avoiding increased circuit complexity. This paper presents the design and the experimental results of an ultra low-power frequency synthesizer for sub-GHz applications. The circuit is based on an integer-N phase-locked loop (PLL) architecture and is implemented in a 90-nm CMOS technology. It includes a LC VCO, which makes use of shunt-connected switched-coupled inductors to provide wideband operation and low power consumption. Moreover, a truly-modular programmable frequency divider adopting true single-phase clocked logic cells (TSPCL) for the first stages was exploited to minimize power consumption. The proposed circuit provides excellent performance in terms of phase noise and spurious rejection while drawing only 1.4 mA from a 1.2-V supply. II. FREQUENCY SYNTHESIZER ARCHITECTURE Fig. 1 shows the simplified block diagram of the proposed frequency synthesizer. The circuit was designed for a low-IF sub-GHz transceiver with a 300-kHz IF frequency. The transceiver operating bands are 300-470 MHz and 750-950 MHz. The frequency synthesizer is implemented by means of a programmable integer-N PLL with the VCO operating at a double and quadruple frequency of the LO tone. This approach takes advantage of integrated inductors with better performance in terms of quality factor and ωQL. The VCO provides two sub-bands, which are selected by a control bit. The lower band is 1.2-1.5 GHz, whereas the higher one is 1.5-1.9 GHz. The operating LO bands are obtained by properly dividing the VCO output. The 300-470 MHz band is obtained dividing by 4 both VCO lower and higher band. The 750-950 MHz band is obtained dividing by 2 the VCO higher band. The LO quadrature signals are generated by means of two source-coupled logic (SCL) divide-by-two circuits, which are inserted out of the PLL loop. A multiplexer is adopted to select the appropriate divide-by-two output. The input interface circuit generates a programmable 300/600-kHz PLL reference employing a fixed 3-MHz input signal. The same bit controls the input interface circuit and the multiplexer to obtain a fixed 150-kHz frequency step in the selected operating frequency band. A programmable integer divider, driven by a 14-bit word, performs channel selection. To Figure 1. Simplified block diagram of the frequency synthesizer. 978-1-4244-6664-1/10/$26.00 ©2010 IEEE 142