2410 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 10, OCTOBER 2010 Dual-k Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs Hasanali G. Virani, Rama Bhadra Rao Adari, and Anil Kottantharayil Abstract—A dual-k spacer concept is proposed and evaluated in underlap and nonunderlap n-channel silicon tunnel field-effect transistors (FETs) for the first time using extensive device sim- ulations. The dual-k spacer consists of an inner layer made of a high-k material and an outer layer made of a low-k material. It is shown that the dual-k spacer improves the performance of n-channel tunneling FETs and more so for the underlap struc- tures. Performance improvements are illustrated and explained for SiO 2 , Al 2 O 3 , and HfO 2 gate dielectrics. The structure is op- timized for the ON-state current without degrading the OFF-state current or the subthreshold slope. Index Terms—Band-to-band tunneling, high-k, subthreshold slope, tunnel field-effect transistor. I. I NTRODUCTION S CALING OF MOSFET in the nanoscale regime is limited by the nonscalability of the subthreshold slope (SS) [1]. This is due to the dependence of the current on the thermal in- jection mechanism which limits the SS to 60 mV/decade at T = 300 K [2]. The tunneling field-effect transistor (TFET) is being extensively studied in the literature, particularly for ultralow- power applications. Since the current depends on band-to-band tunneling, the TFET could have SS less than 60 mV/decade at T = 300 K. This permits low standby leakage currents and enables scaling of V DD . The first TFETs were discussed in the literature as parasitic devices in early MOSFET technology [3]. Banerjee et al. [4] proposed for the first time that the TFET could be a potential candidate to replace MOSFETs in VLSI applications. Recently, Koswatta et al. [5] presented a comparative study of a carbon nanotube (CNT) TFET with conventional MOSFETs. Schmitt- Landsiedel and Werner [6] compared TFET with MOSFET and proposed circuits with a mix of TFETs and MOSFETs. The most widely explored TFET structure is a gated p-i-n structure. The structural similarity of this structure to Manuscript received March 31, 2010; accepted June 22, 2010. Date of publication August 16, 2010; date of current version September 22, 2010. The review of this paper was arranged by Editor M. J. Kumar. H. G. Virani is with the Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India, and also with the Department of Electronics and Telecommunication Engineering, Goa College of Engineering, Farmagudi-Goa, India (e-mail: hgvirani@ee.iitb.ac.in). R. B. R. Adari and A. Kottantharayil are with the Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India (e-mail: anilkg@ee.iitb.ac.in). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2010.2057195 MOSFETs also offers ease of fabrication using standard CMOS technology. Even though TFETs have been experimentally demonstrated with superior SS and subthreshold leakage com- pared to MOSFETs of comparable gate length, the ON-state current (I ON ) remains significantly low, particularly for silicon TFETs [7]–[9]. The drain current in an n-channel TFET (nTFET) is due to the tunneling of valence-band electrons from the source to the conduction band of the i-region. This tunneling current depends on the height and the width of the tunnel barrier. Various tech- niques for enhancing I ON , theoretically studied in the literature, can be classified into two: 1) tunnel barrier height engineering and 2) tunnel width engineering. Tunnel barrier height can be lowered by using a lower bandgap semiconductor [7], [10]– [20]. Various materials investigated are SiGe [10], [21], germa- nium [13]–[15], [21]–[23], various III–V compounds like InAs, InGaAs [13], [14], [19], and CNTs [7], [8], [17], [18]. The second option to enhance the drain current, i.e., tunnel width engineering, can be achieved by enhancing the p-i- junction electric field. The electric field can be enhanced using one or more of the following methods: gate dielectric scaling [20], [24], [25], the realization of devices on ultrathin SOI [26], the underlap drain structure, and the source and drain doping engineering [15], [16]. High-k (hk) spacers have been studied in conventional pla- nar MOSFETs and FinFETs to electrically induce extension regions, and this technique was found to suppress short-channel effects [27], [28]. In our previous work [29], we have shown that, by using an hk spacer, the I ON and SS of an nTFET with a 1-nm SiO 2 gate dielectric are enhanced, without the deterioration of the OFF-state current (I OFF ). In this paper, we have explored the use of a dual-k spacer in TFETs to improve the performance. By using an hk inner spacer and a low-k (lk) outer spacer, the I ON of nTFETs could be improved compared to single-layer spacer devices. The impact of the thickness and dielectric constant of the hk spacer and the k of the gate dielectric on performance is investigated. The underlap structure results in further improvements in the perfor- mance. The physical origin of this improvement is explained. This paper is organized as follows. Section II describes the device structure and simulation setup. In Section III, we present the effect of spacer engineering on performance and explain the underlying device physics. Device optimization using the dual-k spacer is presented in Section IV. The impact of the gate dielectric is also considered in the optimization. In Section V, 0018-9383/$26.00 © 2010 IEEE