A reconfigurable multi-core computing platform for robotics and e-health applications Dennis Majoe 2 , Lars Widmer 1 , Liu Ling 1 , Jim Chih-Chen Kao 1 , Jürg Gutknecht 1 1 ETH Zürich, Switzerland Lars.Widmer@inf.ethz.ch 2 MA Systems and Control Ltd., United Kingdom. dennis.majoe@masystems.co.uk Abstract Increasingly embedded devices are turning to two technologies to achieve high performance and enable efficient programmability as well as product usability. The first is multi-core processing on FPGA devices in which the multi-core architecture allows software to map application-level parallelism to inherent parallel fabric to offer better performance, the re- configurability leads to flexible and adaptive designs. The second is wireless communications that allow sensors to be distributed flexibly across a structure for example in the case of a body area network. This paper describes the ongoing design of a multi RF channel, multi-core embedded design which will be used as a generic FPGA solution to meet the requirements of both e-health applications as well as robotics applications. Keywords: FPGA, e-Health, robotics, embedded systems, reconfigurable multi-core processing, wireless communications. 1. Introduction Embedded applications are becoming more complex requiring higher levels of parallelization and computational complexity. However as they often run on batteries they must be low power and additionally they must be small enough to fit into highly portable or wearable solutions. In this paper the embedded applications focus on robotics and e-Health sensors. In the field of robotics an important aspect is re- configurability both during development for design and debug and post development for functional upgrades. As a reconfigurable device, the field programmable gate array (FPGA) introduces not only the software programmability commonly seen in microcontrollers, but also hardware programmability, that is, the hardware architecture can be fine tailored to the applications. The early use of FPGAs in robotics aimed to achieve highly flexible high speed logic solutions by directly mapping algorithms into the hardware fabric in an FPGA chip. Kale and Shriramwar [1] for example used FPGAs to create highly flexible control algorithms for wheeled robots. This approach of FPGA-based development can offer higher performance in the final system. However, the improved performance is achieved at the penalty of high development costs. The high cost is due to the manual development of the register transfer level (RTL) code for an algorithm and the huge debugging overhead introduced by the long synthesizing and routing time (normally 30 minutes) . To improve the efficiency of FPGA-based system development, a set of general purpose soft RISC processors have been developed and delivered by FPGA vendors. For example, Xilinx’s MicroBlaze™ core [2] and Altera’s Nios II cores. These soft cores and the corresponding compilers provide software programmability that system developers normally see in microcontrollers. Therefore the development process is accelerated by reusing existing software, avoiding RTL programming and avoiding frequent synthesizing hardware during debug time. Eugenio and Estradase [3] made use of the higher functionality and flexibility introduced by a soft computing core implemented on an FPGA and combined this with a Linux OS making for a highly configurable and easily programmable design. Following in the same line several other research projects were conducted using FPGAs in different robots. [4][5]. This improved development efficiency comes at the cost of performance particularly in terms of parallelism. To improve the system performance with the reduced development cost, a configurable multi-core architecture that can address the application-level parallelism in the hardware is often required. Shimai and Tani et al [6] describe a multi core mixed integer quadratic programming solver for mobile robot control. Such multi core parallel computing platforms are essential as the number of parallel tasks increase and a problem may be solved by breaking it up into multiple tasks. In this case the processing is achieved by multiple dedicated computation cores. Sun et al [7] describe a dual core robot controller based on Altera’s Nios II core and Cyclone II FPGA. By specifying a switching fabric to a shared memory, the two processors may execute in parallel on shared data. However in [7], the size of the cores and the prefixed interconnect architecture (the shared memory) limits the parallelism that can be mapped into the hardware. The size of a core limits the number of cores that can be 2012 IEEE/ACIS 11th International Conference on Computer and Information Science 978-0-7695-4694-0/12 $26.00 © 2012 IEEE DOI 10.1109/ICIS.2012.12 449 2012 IEEE/ACIS 11th International Conference on Computer and Information Science 978-0-7695-4694-0/12 $26.00 © 2012 IEEE DOI 10.1109/ICIS.2012.12 457 2012 IEEE/ACIS 11th International Conference on Computer and Information Science 978-0-7695-4694-0/12 $26.00 © 2012 IEEE DOI 10.1109/ICIS.2012.12 457 2012 IEEE/ACIS 11th International Conference on Computer and Information Science 978-0-7695-4694-0/12 $26.00 © 2012 IEEE DOI 10.1109/ICIS.2012.12 457 2012 IEEE/ACIS 11th International Conference on Computer and Information Science 978-0-7695-4694-0/12 $26.00 © 2012 IEEE DOI 10.1109/ICIS.2012.12 457 2012 IEEE/ACIS 11th International Conference on Computer and Information Science 978-0-7695-4694-0/12 $26.00 © 2012 IEEE DOI 10.1109/ICIS.2012.12 451