Distributed Effects in High Power RF LDMOS Transistors Kavita Goverdhanam, Wenhua Dai, Michel Frei, Don Farrell, Jeff Bude, Hugo Safar, M. Mastrapasqua, Tim Bambridge Agere Systems, 1110 American Pkwy, Allentown, PA 18109 Abstract - This paper focuses on the effects of distributed RF transmission lines on performance aspects, such as, gain, output power, efficiency etc. in high power RF LDMOS amplifiers. The methodology to model and capture the distributed effects will be discussed. Suitable alternatives to mitigate power loss due to distributive effects in large transistors will be presented. Also, the contributions of the package to the overall device performance will be addressed. I. INTRODUCTION To meet the needs of the 2.5G and 3G cellular and personal communication systems market, high power RF amplifiers with high output power, power gain, efficiency and linearity are required. Silicon technology has demonstrated that it can meet these needs, especially with the LDMOS [1], [2]. As performance aspects continue to improve, accurate and efficient models from the device level [3] to the package level [4] become very important for circuit designs. For high power devices where the device size increases, the distributed effects have a significant impact on the device performance. Due to this reason, modeling of distributed effects has received a lot of attention [5], [6]. This paper focuses on the effects of distributed metal lines on the performance of large transistors, using the RFLDMOS device as an example. To begin with, the effect of distributed metal topology on the output power of a large transistor is highlighted. Next, the methodology of modeling distributed effects in transistors is discussed and validated. Following this, suitable simple modifications to the metal topology for mitigating power loss in large transistors are proposed. The package plays a crucial role in the device performance and this will be shown as well. II. POWER LOSS IN LARGE TRANSISTORS This study began with the investigation into an unexpected loss of over 20W of power observed in measurement of the performance of a large LDMOS transistor whose output power was calculated to scale to about 70W from the measurements of a scaled smaller device. While it was expected that there would be some deviation from this scaled value of 70W due to losses associated with distributed effects, the extent of losses observed for this particular device/topology was out of the range of what was observed for most other devices with alternate topologies. To understand the mechanism of this power loss, a fullwave distributed Electromagnetics (EM) simulation of the device was undertaken. The topology of the transistor used in this study is shown in Fig. 1. In the figure, the gate and drain rails are metal sections in the lateral (x) direction. The gate and drain trees are metal lines that connect to the gate and drain rails respectively and extend in the longitudinal (y) direction. The gate/drain trees are repeated periodically in the lateral direction. The device investigated here has 21 gate/drain tree pairs. Fig.1 represents the active region as a single sub-device between the each gate-drain tree pair. In reality, the active device is distributed periodically in the longitudinal direction along every tree. The device has a total gate width of 126mm. A fullwave EM simulation of this device in the package environment showed a nonuniform distribution of voltage along the 21 trees. Fig.2. shows the amplitude of the voltage at the gate terminal along each of the 21 sequential trees for this device. Gate Pads x y Gate Tree Drain Tree DRAIN RAIL GATE RAIL 5 10 15 20 1.5 2 2.5 3 3.5 Vg amplitude (V) Sequential Tree # From Fig. 2, it can be seen that the voltage peaks at the center and tapers off drastically at the edges. The net average output power density of this device is 0.41 W/mm. Thus for a device with a gate width of 126mm, the distributed model of the device with the package leads to approximately 50W power at 1dB gain compression (P1dB). The loss in power is also observed Fig. 2: Amplitude of gate voltage at 2.1GHz for the sequential trees of LDMOS device shown in Fig.1 Fig. 1: Schematic of Distributed Transistor Model