Effect of Static Power qissipation in Burn-in Environment on ~ield of VLSI Arman Vassighi ECE Department Univ .of Waterloo Waterloo,Canada Oleg sem ~ nov ECE Depa tment Univ.ofW terloo Waterloo,C nada Manoj Sachdev ECE Department Univ.of Waterloo Waterloo, Canada Ali Keshavarzi Research Labs Intel Gorp. Hillsboro, OR Abstract The leakage power is expected to inc ease with scaling of CMOS technology. The increased leakage is a strong function of the elev ted temperature and voltage stress. As a consequence, under the bum-in (BI) conditions the levated leakage power may cause increased post Burn- in fallout. In this paper the impact elevated leakage and technology scaling in bum-in environment on post BI yield is analy ed. We have also shown that to maintain a constant post-BI yield loss, the burn-in tempe ature should go down by lO°C for each technology generation. We also show that at stati burn-in conditions, the die temperature is increased exponentially and range of optimal st essed voltage and temperature for fixed post bum-in yield loss is reduced significantly, whe CMOS technology is aggressively scaled down. 1: Introduction Burn-in (BI) is an important test t chnique to weed out infant mortality from the main population. As a result, quality and eliability of outgoing Integrated Circuits (ICs) are improved. During the BI, ICs are subj cted to elevated voltage and temperature stress. As a consequence, the field and temperat re enhanced failure mechanisms are accelerated [1]. Optimization of effectiveness of BI test has been the constant focus of quality and reliability engineers. As we scale the transistor to deep s b-micron regime, it's off state leakage increases sig- nificantly. A linear reduction in transis or threshold voltage with technology scaling, results in exponential increase in its leakage. This leakage is further increased under voltage and temperature stress conditions. High 1 akage causes further elevation in chip temperature and eventually leads to a positive feed ack. Therefore, handling the power dissipation, be- comes an important consideration duing the burn-in. In this article, we investigate static power dissipation as a function of tern erature and voltage. The objective is to minimize the burn-in temperature and voltage, hile maintaining constant yield during the burn-in test for future technologies. Proceedings of the 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’02) 1063-6722/02 $17.00 © 2002 IEEE