High Performance Asynchronous Bit-Level Parallel Interface for Board-to-Board Inter Processor Communication Faizal Arya Samman 1 Dept. of Electrical Engineering Faculty of Engineering, Universitas Hasanuddin Kampus Gowa, Jl. Poros Malino Km. 20, Borongloe 92172 Email: faizalas@unhas.ac.id 1 Thagiat Ahzan ADP 2 and Fandhi Nugraha 3 Dept. of Electrical Engineering Faculty of Eng., Universitas Hasanuddin Email: ahzanadp@yahoo.co.id 2 fendhinugraha@gmail.com 3 Abstract—This paper presents a bit-level parallel communi- cation interface used for inter processor communication sepa- rated on different printed circuit boards. A high performance board-to-board communication interface is important in modern supercomputers and portable computers or gadgets with multiple screen displays. We propose a recalibrated transmitter and re- ceiver soft IP cores to support asynchronous handshake commu- nication interface. The valid signal can be delayed for a few cycle to guarantee the metastability of data signals. The tuning of the delay can be recalibrated and tested during pre-implementation step. The flexibility to tune a correct valid delay time, which is set as minimum as possible as far as the data integrity can be guaranteed, enables the operation the communicating devices at its maximum performance. The proposed technique has been simulated using HDL-level simulation and has shown its expected performance with four testing scenarios. Keywords—Bit-parallel communication, Asynchronous commu- nication interface, HDL Simulation, Transceiver, FPGA, IP core I. I NTRODUCTION Data communication is an important part of the nowadays information and communication technology industries. Most of devices are concerned with the transmission of data or information. Computers, gadget and other devices transmit data through a medium, wired or wireless. The need for high performance media access control protocol is a must in order to guaranteed the consumer satisfaction. The transmission bandwidth capacity or required between any two points in a point-to-point circuit depends on the average traffic conditions to be carried [1]. Data transmission between two or more devices, according to the data bit width, can be divided into two class, namely, bit serial and bit parallel communication. Serial communication is the process of transmitting and receiving data sequentially bit-by-bit. There are many commonly used serial communi- cations, they are PS2, UART, I2C, SPI and USB, where all of them have been even standardized. PS2 is usually used as a communication interface between microcontroller with other devices such as mouse and keyboard. However, this communication protocol standard has been nearly obsolete, and replaced by USB. UART is commonly used to communicate data between two processors [2]. I2C and SPI commonly used for communication on inter-chip or inter-chip low-medium speed data-stream transfers such as ADC with microcontroller and sensor with microcontroller [3] [4], [5]. USB is the most common communication interface today. we can find it on port computer, printer port, mouse, keyboard and others. In bit-level parallel communication, data transmission can be accomplished as much as N-bits through an N-bits data path. Thus, data transmission becomes faster, but on the other hand, the logic gate area becomes higher. The bit-level parallel communication interface is required for the transmission of large amounts of data and in a short time. To implement this, a standard module is required that ensures stability, reliability, and is able to work effectively in improving the work efficiency. The development of board-to-board communication has its own challenges, namely metastability, crosstalk, and cross domain clock. Metastability is concerned with problem called data signals stability on a data path, which cannot be read before all data signals haven been in a steady-state condition. Accessing the data before the metastability is guaranteed can cause the lose of data integrity and validity. To solve this problem we can use an open loop or closed loop method with synchronizer. Meanwhile, we use a valid signalling method to ensure that the data have been steadily loaded before the recipient node read them from the physical link. Data processing capability of a system depends not only on data processing devices but also influenced by data communi- cation interface. The communication interfaces are connected directly to the physical links of between two communicating devices on each separated board. The bottleneck performance presented in the physical link will lower the system per- formance, regardless the higher working frequency speed of devices or processing elements. Hence, board-to-board data communication is important aspect in a high performance com- puting system, as it is also discussed in this paper. Supercom- puters or high performance computers implemented on a huge number of rack boxes, and smart gadgets implemented with multiple display screens in different boards are good examples of the board-to-board inter processor data communication. 978-1-5386-2708-2/17/$31.00©2017/IEEE 2017 International Seminar on Intelligent Technology and Its Application 397