Continuos Time ΣΔ modulator with efficient gain compensated integrators Victor R. Gonzalez-Diaz a,n , Aldo Pena-Perez b , Franco Maloberti c a Faculty of Electronics, Benémerita Universidad Autónoma de Puebla, Av. San Claudio y 18 Sur, Col. Jardines de San Manuel, Puebla, Mexico b MCU Division, Microchip-Atmel Corporation, 1600 Technology Drive, San Jose, CA, United States c Laboratorio di Microsistemi Integrati, Università Degli Studi di Pavia, Via Ferrata 1, Pavia, Italy article info Article history: Received 14 October 2015 Received in revised form 26 May 2016 Accepted 2 August 2016 Keywords: Sigma-delta modulators Analog IC design DC-gain Compensation abstract This paper presents the design of a second-order continuous time (CT) ΣΔ modulator with DC gain compensated OTA based integrators. Compared to similar solutions, this novel technique uses a simple transconductor stage to compensate for the multi-bit feedback DAC inputs in the modulator. The work details the effective compensation technique by using a negative transconductance stage that only in- creases a 17% of the overall ΣΔ power consumption. The compensated CT modulator is implemented in a 65 nm CMOS process and achieves a SQNR of 79.3 dB and a state-of-the-art FoM of 31 fJ/conv-level. & 2016 Elsevier Ltd. All rights reserved. 1. Introduction In spite of the new Integrated Circuit (IC) manufacturing pro- cesses, the operational transconductance amplifier (OTA) is still a paramount circuit for many mixed signal processing systems such as ΣΔ Analog to Digital Converters (ADCs). Compared to the Dis- crete Time (DT) counterparts, Continuous Time (CT) ΣΔ mod- ulators relax the amplifier's bandwidth (BW) and increase the operating speed of the modulator [1,2]. With nanoscaled tech- nologies, it is possible to design amplifiers with large bandwidth to minimize the excess loop delay impact in CT ΣΔ modulators, transforming to the finite OTA's bandwidth as a minor source of nonideal behavior. On the other hand, to achieve a high DC gain for the OTA is difficult since the channel's output resistance of a MOS transistor drops significantly in nanometer technologies [3,4]. To increase the amplifier's Gain Bandwidth (GBW) product there are multistage amplifiers but these open new limitations for stability and voltage headroom that negatively impact to the ΣΔ modulator [5]. In resume, maximizing the OTA GBW requires topologies that consume more power and limit the advantage of a CT im- plementation for the ΣΔ ADC. One alternative solution to the OTA limits is the inverted based integrator for ΣΔ modulators with the corresponding disadvantages of pseudodifferential architectures [6–8]. Another possibility for CT signal processing is to use large BW but low DC gain fully differential OTAs and compensate for the possible nondesirable effects. The approach has been explored more extensively for DT implementations. This paper describes new implementation insights for the CT OTA DC gain compensa- tion technique. Compared to the existent solutions, the proposed compensation stage does not significantly increase the system costs in CT ΣΔ modulators. The paper is organized as follows: Section 2 resumes the principal works in OTA DC gain compensation techniques and highlights the contribution of this work. Section 3 presents the proposed compensation technique and Section 4 discusses the implementation on a single stage amplifier. For validation pur- poses, Section 5 presents the Bulk CMOS 65 nm transistor level simulation results on a second-order feedforward CT ΣΔ mod- ulator. Finally Section 6 draws conclusions. 2. State-of-the-art OTA DC gain compensation techniques The OTA limited DC gain makes an integrator to deviate from the desired response, giving rise to magnitude and phase errors as function of the frequency (a leakage integrator). The OTA DC gain compensation has been explored in the past for diverse analog circuits, including compensation techniques for ΣΔ modulators. This section resumes the most important compensation schemes for the Discrete Time and Continuous Time implementations to emphasize the contribution of this work. Fig. 1 synthesizes the compensation techniques evolution with some of the most relevant topologies. In first place, the lossless Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/mejo Microelectronics Journal http://dx.doi.org/10.1016/j.mejo.2016.08.003 0026-2692/& 2016 Elsevier Ltd. All rights reserved. n Corresponding author. E-mail address: vicrodolfo.gonzalez@correo.buap.mx (V.R. Gonzalez-Diaz). Microelectronics Journal 56 (2016) 38–45