Noise Analysis of a Reduced Complexity Pipeline Analog-to-Digital Converter Hai Phuong Le, Aladin Zayegh, Jugdutt Singh School of Electrical Engineering Victoria University PO BOX 14428, Melbourne City MC 8001, Australia E-mail: hai@ee.vu.edu.au. Abstract This paper presents a mathematical analysis of the noise generated within a 12-bit reduced complexity pipeline Analog-to-Digital converter (ADC) to demonstrate the effect of noise on the device performance. A modified flash ADC was employed instead of the traditional full flash ADC to implement the sub-ADC in the proposed pipeline ADC to reduce the device complexity and attain lower system power consumption. The 12-bit pipeline ADC is operated at 400MHz and generates total noise power of 3.38 10 -12 f (V 2 ) at this frequency. The developed model provides a good estimation of the noise generated by the circuit and gives an accurate prediction on the circuit noise performance. Also, such model provides good guide for further improvement of the circuit performance. 1. Introduction Analog-to-Digital converters (ADCs) are the most essential part in any signal processing systems and other data acquisition systems because they are the boundary between the analog and digital signal processing. The function of an ADC is to transform an analog signal into equivalent digital data for further storage and processing. Since the mid-1970s, ADCs have been widely designed using integrating, successive approximation, flash, delta- sigma techniques. More recently, there has appeared a new class of ADC with an architecture known as pipeline, which offered an attractive combination of high speed, high resolution, low power dissipation and small die size. The pipeline ADC, therefore, became the optimum solution for present low power applications, such as a wireless communication system [1]. However, when working at high frequencies, the noise generated within the pipeline ADC itself will play an increasingly important role in its overall performance. The existence of noise in CMOS integrated circuits is basically due to the fact that electrical charge is not continuos but is carried in discrete amounts to the electron charge, and thus noise is associated with fundamental processes in the integrated-circuit devices [2]. A detailed analysis on the noise performance of the device, therefore, is essential. Fig 1 shows a typical pipeline scheme. A pipeline ADC basically consists of numerous consecutive stages, each stage contains a sub-ADC, an inter-stage sample- and-hold circuit (SHC), a sub-digital-to-analog converter (sub-DAC), and a substractor that includes an amplifier to provide gain, as illustrated in Figure 1. Each stage generates a coarse m i -bit. The final stage, however, only includes an inter-stage SHC and a fine ADC since no analog conversion will be required [3]. To obtain 12-bit resolution, the pipeline ADC is designed to have three stages, each stage contributes 4-bit resolution. Figure 1. Pipeline ADC Architecture This paper presents a mathematical model of noise in a 12-bit pipeline ADC to demonstrate the effect of noise on the device performance. The model provides the Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications (DELTA’04) 0-7695-2081-2/04 $ 20.00 © 2004 IEEE