Variability-Aware Reliability Simulation of Mixed-Signal ICs with Quasi-Linear Complexity Elie Maricau and Georges Gielen ESAT-MICAS, KULeuven, Belgium elie.maricau@esat.kuleuven.be Abstract—This paper demonstrates a deterministic, variability- aware reliability modeling and simulation method. The purpose of the method is to efficiently simulate failure-time dispersion in circuits subjected to die-level stress effects. A Design of Experiments (DoE) with a quasi-linear complexity is used to build a Response Surface Model (RSM) of the time-dependent circuit behavior. This reduces simulation time, when compared to random-sampling techniques, and guarantees good coverage of the circuit factor space. The DoE consists of a linear screening design, to filter out important circuit factors, followed by a resolution 5 fractional factorial regression design to model the circuit behavior. The method is validated over a broad range of both analog and digital circuits and compared to traditional random-sampling reliability simulation techniques. It is shown to outperform existing simulators with a simulation speed improve- ment of up to several orders of magnitude. Also, it is proven to have a good simulation accuracy, with an average model error varying from 1.5 to 5 % over all test circuits. I. I NTRODUCTION Scaling towards smaller transistor sizes in order to achieve smaller, faster, lower power and less expensive chips, creates evermore design problems. Die level reliability issues (e.g. Negative Bias Temperature Instability (NBTI) and Hot Carrier degradation (HC)) and increasing process variability are at the forefront of problems to be dealt with in modern and future CMOS technologies [1]. The effect of transistor ageing (i.e. NBTI and HC) on circuit behavior, especially when combined with process variability, is very complicated and not always well understood. The lack of adequate knowledge about circuit ageing can cause unreliable products or unnecessary design margins. Existing solutions (e.g. post-production accelerated stress testing) become too expensive due to an increasing demand for very low failure rates augmented with evermore reliability and variability problems. A designer needs a statistical circuit analysis tool that includes circuit ageing. Such a tool must be fast (i.e. no more than a few hours of simulation time, even for large circuits) but must also have a good simulation accuracy. Moreover, a designer must be able to extract infor- mation (i.e. weak-spot detection) to improve his design or to implement countermeasures (i.e. circuit tuning). In literature, most reliability simulation methods have been developed a few years ago and are therefore intended for CMOS technologies where variability was not yet an issue [2], [3]. To make a reliable design in a sub 90nm technology, however, this is no longer satisfactory. Bestory et al. [4] did include the effect of variability, using a Monte-Carlo (MC) simulation wrapped around a nominal reliability simulator based on high-level behavioral transistor models. This approach is fast, but it lacks accuracy, especially for analog circuits where the effects of time-varying stress voltages are important. In previous work [5], the authors presented a more accurate reliability simulator able to cope with time-varying stress. In this work, the authors also used a MC-approach in order to include variability effects. But, although an MC-based reliability simulation is accurate, it also has a large number of disadvantages: i) It is very cpu intensive. ii) There are no weak-spot detection capabilities. And iii) the simulation has to be rerun every time new or extra process data is included. In this paper, a reliability modeling and simulation method to tackle the before-mentioned problems is presented: 1) The method is systematic and applicable to analog, digital and mixed-signal circuits. 2) A set of experimental designs ensures the generation of valid, defensible and accurate engineering conclusions. 3) A screening design identifies circuit weak spots and reduces circuit simulation time guaranteeing a quasi- linear complexity. 4) A regression design enables the generation of a circuit Response Surface Model (RSM) of the circuit behavior as a function of time. The method, presented in this work, is built around a nominal reliability simulator, the authors presented earlier [5]. A brief review of this work is given in section II. The variability-aware simulation framework is introduced in section III. Section IV presents experimental simulation results and compares the results with random-sampling based techniques. Finally conclusions are drawn in section V. II. NOMINAL RELIABILITY SIMULATION The core of a reliability simulator is a method to calculate the ageing of a circuit with fixed design parameters (i.e. without process variability). Following subsections give a brief overview of both the simulation method and the degradation models used in this work and described in more detail in work presented elsewhere [5], [6]. A. Simulation Methodology Most degradation effects have an exponential dependence on the transistor gate voltage. Therefore, time-varying stress volt- ages have to be included when calculating circuit degradation. To obtain accurate information about the time-varying stress 978-3-9810801-6-2/DATE10 © 2010 EDAA