1314 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 6, JUNE 2006 A Highly Linear and Efficient Differential CMOS Power Amplifier With Harmonic Control Jongchan Kang, Jehyung Yoon, Kyoungjoon Min, Daekyu Yu, Joongjin Nam, Youngoo Yang, Member, IEEE, and Bumman Kim, Senior Member, IEEE Abstract—A 2.45 GHz fully differential CMOS power amplifier (PA) with high efficiency and linearity is presented. For this work, a 0.18- m standard CMOS process with Cu-metal is employed and all components of the two-stage circuit except an output transformer and a few bond wires are integrated into one chip. To improve the linearity, an optimum gate bias is applied for the cancellation of the nonlinear harmonic generated by and a new harmonic termination technique at the common source node is adopted along with normal harmonic termination at the drain. The harmonic termination at the source effectively suppresses the second harmonic generated from the input and output. The ampli- fier delivers a 20.5 dBm of with 17.5 dB of power gain and 37% of power-added efficiency (PAE). Linearity measurements from a two-tone test show that the power amplifier with the second harmonic termination improves the IMD3 and IMD5 over the amplifier without the harmonic termination by maximally 6 dB and 7 dB, respectively. Furthermore, the linearity improvements appear over a wide range of the power levels and the linearity is maintained under 45 dBc of IMD3 and 57 dBc of IMD5 when the output power is backed off by more than 5 dB from . From the OFDM signal test, the second harmonic termination improves the error vector magnitude (EVM) by over 40% for an output power level satisfying the 4.6% EVM specification. Index Terms—Differential power amplifier, error vector magni- tude (EVM), even in-phase harmonics, harmonic termination, odd anti-phase harmonics, Volterra series. I. INTRODUCTION A S THE PROLIFERATING wireless personal communica- tion systems require multi-function capability with minia- turization, the CMOS process, which has the merit of high-level integration, becomes the technology of choice for the solution. With the continued scaling of CMOS technology, the multi- function RF transceivers including the baseband and IF blocks, could be integrated in a single chip. Many efforts have also been made to implement RF CMOS power amplifier (PA) [1]–[3] and integrate it with RF transceivers [4]–[6]. However, it is still a challenge for CMOS PA to be competitive with compound Manuscript received September 20, 2005; revised February 16, 2006. This work was supported in part by the Korean Ministry of Education under BK21 project and the Center for Broadband OFDM Mobile Access (BrOMA) at POSTECH through the ITRC program of the Korean MIC, supervised by IITA (IITA-2005-C1090-0502-0008). J. Kang was with the Department of Electrical Engineering, Pohang Uni- versity of Science and Technology (POSTECH), Pohang, Kyungbuk 790-784, Korea, and is now with Handsets Research Center, LG Electronics, Seoul 153- 801, Korea. J. Yoon, K. Min, D. Yu, J. Nam, and B. Kim are with the Department of Elec- trical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Kyungbuk 790-784, Korea (e-mail: bmkim@postech.ac.kr). Y. Yang is with the School of Information and Communication, Sungkyunkwan University, Suwon 440-746, Korea. Digital Object Identifier 10.1109/JSSC.2006.874276 Fig. 1. Simplified structure of unit cell. semiconductors-based PA. For competitiveness, the CMOS PA needs to overcome poor device reliability and ruggedness prob- lems due to its low breakdown voltage. Many published papers show reasonable power performances with switching CMOS PA, but the operation with large voltage swings are still a reliability concern. The full integration of CMOS PA has progressed steadily [7], [8] but signal coupling due to the highly conductive substrate may prohibit the integration of PA with other blocks. The coupled signal from the PA can be large enough to saturate the low-noise amplifier (LNA) and dis- turb the oscillation frequency of the voltage-controlled amplifier (VCO) (load pulling effect). To reduce the coupling problem, a fully differential circuit topology should be adopted instead of the single-ended PA. In a fully differential topology, the current is dumped to the ground twice per a cycle and the substrate noise components at the signal frequency are suppressed while the second harmonic remains, resulting in a reduced interference. Considering the points mentioned above, an IEEE 802.11 WLAN may be the most suitable application for the CMOS PA. Since they operate at a comparably low power level with a low voltage swing , the burden of the reliability and ruggedness is significantly reduced. Additionally, the time division duplexing (TDD) mode of the 802.11 WLAN helps the integration with the transceiver since a TDD-based system does not concurrently operate both the receiver and transmitter parts. This confines the substrate coupling problem to the transmitter. A tight error vector magnitude (EVM) specification for the high speed data communication and the over-10-dB peak-to-average-power ratio (PAR) of the OFDM signal re- quire extremely high linearity over a broad power range below . Furthermore, these requirements impede obtaining high power-added efficiency (PAE) and lower the battery life. In this paper, we present a highly linear and efficient CMOS PA operating at 2.45 GHz. To secure the high linearity, the gate 0018-9200/$20.00 © 2006 IEEE