Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip Maurizio Palesi † , Fabrizio Fazzino †,‡ , Giuseppe Ascia † , and Vincenzo Catania † † DIIT, University of Catania, Italy ‡ Simply RISC LLP, Bristol, UK {mpalesi,ffazzino,gascia,vcatania}@diit.unict.it Abstract—As the number of cores in a chip increases, the role played by the communication system becomes more and more central. An on-chip communication infrastructure based on the Network-on-Chip (NoC) paradigm is today recognized as the most effective and scalable solution able to deal with the communication issues that will characterize the next generation of many-cores architectures. An ever more significant fraction of the overall chip area is devoted to support advanced and reliable communication protocols making the energy resources used for communication starting to compete with the ones spent for computation. Amongst the communication resources, as technology shrinks, the power ratio between NoC links and routers increases making the links becoming more power- hungry than routers. In this paper we propose a novel end- to-end data encoding scheme which exploits the wormhole technique commonly used in NoC-based system to reduce power dissipated by the NoC links. We assess the proposed encoding scheme on a set of representative data streams showing that it is possible to reduce the power contribution of both the self switching activity and the coupling switching activity in inter-routers links. As results, we obtain a reduction in total power dissipation and energy consumption up to 26% and 9% respectively without any significant degradation in terms of both performance and silicon area. The encoder and decoder logic is integrated in the network interface and is transparent to the underling NoC. Keywords-Network on Chip; Low power; Data encoding; Coupling capacitance; Power analysis. I. I NTRODUCTION As the number and heterogeneity of cores into a system- on-a-chip (SoC) increases, the use of an adequate communi- cation infrastructure based on the Network-on-Chip (NoC) paradigm is generally seen as the most effective solution to deal with the complexity of designing next generation of many-cores architectures. The importance of interconnects in complex many-cores chips has outrun the importance of transistors as a dominant factor of performance, power, cost and reliability [1]–[3]. Sophisticate on-chip communication protocols, involving advanced adaptive routing algorithms, selection policies, data protection schemes and mechanisms aimed at guarantee the quality-of-service are pushing the interconnect system to become one of the main elements which characterizes the system in terms of both power dissipation and energy con- sumption. For instance, in the the Intel’s 80-tiles TeraFLOPS processor [4] the communication power is significant at 28% of the tile power and the synchronous tile-level clock distribution accounts for 11% of the total. Energy consumption and power dissipation are today recognized as the most important design optimization objec- tives. The first has important implications on the time-life of a battery driven mobile system, the second represents the dominant factor for thermal and reliability issues. In this paper we propose the use of data encoding tech- nique as a viable way to reduce both the power dissipation and energy consumption due to the links of a NoC. Differ- ently from [5] we propose an end-to-end encoding scheme which exploits the wormhole switching technique and which is transparent to the NoC (i.e., it does not require the re- design of routers and links). In addition, differently from the bus-invert (BI) coding [6] and the coupling driven bus invert (CDBI) coding [7] our encoding scheme reduces the power dissipated by the link taking into account both the contribution of the self switching activity and of the coupling switching activity. The encoder and the decoder are hosted into the network interface (NI). The encoder transmits each flit (except the header flit) as is or inverted, where the decision to invert the data or not is based on the combined contribution in power of both the self switching activity and the coupling switching activity in the links belonging to the routing path; at the end of this path the decoder will then restore the initial data in a transparent way. We assess the proposed encoding scheme and architecture on a set of representative data streams. We compare the proposed approach with the bus-invert coding [6] and the coupling driven bus invert coding [7] as they have the highest potential for power saving while still represent a feasible implementation for on-chip communication. The comparison embraces not only the power/energy figures but also the implications on silicon area and delay due to the overhead of the encoder/decoder logic in the NIs. We show that the proposed data encoding scheme outperforms the other proposals allowing to save up to 26% in power dissipation and 9% in energy consumption. The rest of the paper is organized as follows. In Section II we discuss related research work. A general overview of the proposal is given in Section III. The proposed encoding scheme along with the architecture of the encoder and logic 2009 12th Euromicro Conference on Digital System Design / Architectures, Methods and Tools 978-0-7695-3782-5/09 $25.00 © 2009 IEEE DOI 10.1109/DSD.2009.203 119