XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE Logarithmic Neural Network Data Converters using Memristors for Biomedical Applications Abstract— Data converters are ubiquitous in electrical data driven systems, where they are heterogeneously distributed across the analog-digital interface. Unfortunately, conventional data converters trade off speed, power, and accuracy. Logarithmic analog-to-digital/digital-to-analog converters (ADC/DACs) are employed in biomedical applications where signals with high dynamic range are recorded. For the same input dynamic range of a linear ADC/DAC, a logarithmic one can efficiently quantize the sampled data by reducing the number of resolution bits, sampling rate, and power consumption, albeit with reduced accuracy for high amplitudes. Previously, we employed novel neural network architectures to design smart data converters that could be trained in real-time for general purpose applications, breaking through the speed- power-accuracy tradeoff, and using machine learning techniques and memristors for synaptic realization. In this paper, we report the results of SPICE simulations performed to train our converters to perform logarithmic quantization. The proposed architecture achieved a 77.19 pJ/conv FOM, 2.55 ENOB, 0.26 LSB INL, and 0.62 LSB DNL. These promising features will pave the way towards adaptive human-machine interfaces with continuous varying conditions for precision medicine applications. Keywords— Analog-to-digital/digital-to-analog conversion, biomedical applications, adaptive systems, memristors, machine learning, neuromorphic computing, logarithmic quantization. I. INTRODUCTION For several biomedical applications, such as cochlear implants [1], hearing aids [2], neural recording and stimulation [3-7], a nonlinear analog-to-digital converter (ADC) seems a more appealing choice for a signal processing system than a linear ADC. Audio signals, for example, are well-suited to log encoding because the human ear is less able to distinguish sound levels when the dynamic range of the signals is larger. The benefits of a nonlinear ADC include the ability to handle input signals with a large dynamic range [1- 5], reduction of noise and data bit-rate [6], and compensation for nonlinear sensor characteristics [8]. A logarithmic ADC performs conversions with non-uniform quantization, where small analog amplitudes are quantized with fine resolution, while large amplitudes are quantized with coarse resolution. Unfortunately, the intrinsic speed-power-accuracy tradeoff in linear ADCs is pushing them out of the application band of interest [9]. Furthermore, with the continuous downscaling of technology motivated by Moore's law, this tradeoff has become a chronic bottleneck of modern systems design due to deep sub-micron effects. Those effects are poorly handled by technology-dependent design techniques that overload data converters with enormous overhead, exacerbating the tradeoff and severely degrading their performance [9]. Moreover, conventional data converters lack design standards and are customized with sophisticated design flow. Thus, their architectures are optimized for special purpose applications, from high-speed to high-resolution to low-power [9]. These methods not only require exhaustive characterization and massive validation, but they are also expensive to develop, with a long time-to-market. This paper takes a novel systematic approach to design data converters capable of reconfigurable quantization and logarithmic encoding. The converted data can be used, based on our previous work [9-11], to train the converter to autonomously adapt to the exact specifications, including quantization scale, of the running application and adjust to environmental variations, as shown in Fig. 1(a). This approach will reduce the time to market, efficiently scale with newer technologies, drastically reduce cost, standardize the design flow, and enable a generic architecture for general purpose applications. While practical applications require large-scale linear quantization, small-scale logarithmic quantization is sufficient. We believe that these promising features will substantially increase the number of adaptive converters in low-power wearable monitoring devices for precision medicine applications. We propose a three-bit logarithmic ADC/DAC design. The proposed trainable data converters are based on memristive technology [9] and utilize machine learning (ML) algorithms to train an artificial neural network (ANN) architecture. With their synapse-like behavior, memristors are becoming increasingly prevalent in the design and realization of ANNs [10]. Their small footprint, analog storage properties, low energy consumption, and non-volatility allow them to mimic synapses, where the conductance of the memristor is considered as the synaptic weight [12]. The remainder of this paper is organized as follows. Section II provides background on the logarithmic data conversion theory, evaluation terminology and methodology. Section III presents the proposed ANN logarithmic data conversion and circuit design. In Section IV, the proposed trainable logarithmic data converters are evaluated. The paper is summarized in Section V. II. LOGARITHMIC DATA CONVERTERS A. Logarithmic ADC An N-bit logarithmic ADC converts an analog input voltage (Vin) to an N-bit digital output code (Dout=D N-1 ,…,D 0 ) according to a logarithmic mapping described by ∑ ܦ ௜ 2 ௜ ேଵ ௜ୀ଴ = ଶ  ௖ ݋ ஻ ቀ ௏ ೔೙ ௏ ಷೄ ܤ ௖ ቁ, (1) where N is the number of bits, B is the base of the logarithmic function (e.g., 10), C is defined as the code efficiency factor [7], and V FS is the full-scale analog input voltage range. Larger values of C result in more logarithmic conversion, capturing smaller signals and a higher dynamic range. Eq. (1) implies that the logarithmic ADC achieves good resolution for small input signals, but still allows coarsely quantized large input signals. Quantization noise is thus lower when the signal amplitude is small, and it grows with the signal amplitude. In contrast to an N-bit linear ADC, which has a fixed LSB size of  ிௌ /2 ே , the LSB size of an N-bit logarithmic ADC varies with the input amplitudes, as shown Loai Danial, Kanishka Sharma, Shivansh Dwivedi, and Shahar Kvatinsky Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion - Israel Institute of Technology, Haifa 3200003, ISRAEL, Email: sloaidan@campus.technion.ac.il